====== flink, Universal Serial Interface to FPGA's ======

<box blue right 38% | **Downloads**>
  * [[https://github.com/flink-project/ | flink on Github]]
</box>
flink is ..
  * an universal serial interface to FPGA's
  * a collection of useful blocks in a FPGA
  * open-source
  * highly flexible
  * real-time capable

flink can be read as //fast link// or as the German "flink" meaning fast. It enables any processors to communicate with an external FPGA over a parallel interface (e.g. PCI, EIM, LPB, AXI) or serial interface (e.g. SPI). The FPGA may contain several blocks such as counters or pulse-width modulation. Such blocks are extensively used in robotics for control applications. \\
flink was developed at and is maintained by the Institute of Computer Science at [[http://www.ost.ch|OST]].

===== Overview =====
<box green right 38% | **flink Modules**>
  * [[.:flink_vhdl|flink VHDL subdevices and interfaces]] 
  * [[.:flink_linux|flink Linux Kernel Modules]] 
  * [[.:flink_lib|flink Userspace Library]]
  * [[.:flink_liblite|flink Userspace Library Lite]]
  * [[.:flink_utils|flink Utilities]]
  * [[.:flink_python|flink Python Wrapper]]
  * [[.:flink_deep|flink Java Library]]
</box>

flink can be used on a multitude of targets and with various setups. \\
flink includes the following modules
  * flinkVHDL: Configuration for an external FPGA toghether with a suitable hardware link
  * flinkLinux: Kernel Modules
  * flinkLib: Userspace library for C/C++
  * flinkLite: Userspace library for OS-less systems for C/C++
  * flinkUtils: Utilities and test programs for the flink library
  * flinkPython: Python wrapper
  * flinkDeep: Library for Java 

==== Typical use with C/C++ under an operating system ====
<box red right 38% | **First Steps and Examples**>
  * [[flink_first_steps|flink First Steps]] 
  * [[flink_example_1|flink on a Phytec PCM032 Board]] 
  * [[flink_example_2|flink on a Digilent ZYBO]] 
</box>

Implement all necessary hardware modules with [[flink_vhdl|flink VHDL modules and interfaces]] and choose a suitable interconnection with the available [[flink_linux|flink Linux Kernel Modules]]. Develop your application using the [[flink_lib|flink Userspace Library]]. The following picture shows the system setup.
[{{ flinkoverviewlinux.png?500 | //flink with OS and C/C++ programming//}}]

===== System Architecture =====
An external FPGA contains hardware modules, which provide certain functions such as a pwm generator or an analog input channel. Such an external FPGA is represented by a ''flink device''. Every ''flink device'' contains one or more ''subdevices''. A ''subdevice'' represents a function. At last every ''subdevice'' has one or more ''channels''.
  * **device**: An external FPGA, group of subdevices.
  * **subdevice**: Modul with a specific function, such as ''digital IO'' or ''analog input''.
  * **channel**: Single channel of a subdevice, corresponds to a single pin of a ''digital IO'' subdevice.

[{{ systemarchitectureexample.png?600 | //System architecture for an example system with a motor drive. The drive controlled by an analog output signal. The motor position is determined with a counter module. //}}]

===== Memory Mapping =====
Every subdevice which is specified in a device offers a standardised memory interface towards the driver library. The first 16 bytes comprise the header information which is read-only.

^Offset^Size [byte] ^Name^r/w^Const^Description^
|0x00|4|function|r|yes|function, which this subdevice implements|
|0x04|4|memory size|r|yes|total memory size of this device, including header, subheader and subdevice specific information|
|0x08|4|nof channels|r|yes|number of channels of this subdevice|
|0x0c|4|unique id|r|yes|id identifying this subdevice|

The field ''function'' has the following meaning:
|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
|  function id  ||||||||||||||||
|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|  subtype id  ||||||||  interface version  ||||||||

All the available functions can be found in [[subdevices|Available Subdevices]]. Next comes a subheader. It contains a configuration and status register. The meaning of the single bits of these registers can vary according to the function of the subdevice.

^Offset^Size [byte] ^Name^r/w^Const^Description^
|0x10|4|status|r|no|status of subdevice|
|0x14|4|configuration |r/w|no|configuration word for subdevice|
|0x18|4| | | |reserved|
|0x1c|4| | | |reserved|

Header and subheader is followed by a subdevice specific part. The content varies according to the function and is listed in [[subdevices|Available Subdevices]]