Multiple subdevices with the same number of ports

If multiple subdevices of the same type, same number of ports and different unique_id in addition to a subdevice of the same type and different number of ports is used, an error occurs. The following pages explain, how this error can be resolved.

Error description

The synthesis of the system throws following, or similar, errors in Quartus:

 Error (10652): VHDL Assertion Statement at test01_gpio_block_0.vhd(55): assertion is false - report "Supplied generics do not match expected generics" (FAILURE or ERROR)

Error (12152): Can't elaborate user hierarchy "test01_gpio_block_0:gpio_block_1"

Cause

Because the ports of the subdevice are identical, Qsys creates only one component (block) and uses multiple instances of this component. But each subdevice has a unique id, which is why each subdevice needs a different component. Qsys generates an *.vhd file for each component with a name like test01_gpio_block_0.vhd.

Solution

Create the missing components manually and integrate them in the generated system. An existing component can be copied and modified.

1.) Generate the system in Qsys

Generate the system in Qsys

2.) Copy and modify the components

Go to the folder synthesis, where Qsys created the files for the system
For each group of subsystem with identical ports there is one *.vhd-file. For Example test01_gpio_block_0.vhd. In the following text this file(s) is/are called template.
For each member of such a group create a copy of the template(s) and renumber them accordingly. For Example: test01_gpio_block_0.vhd is the original and test01_gpio_block_1.vhd is the copy
In each copy 7 lines has to be modified:

The name of the entity at the beginning of the entity declaration
```
test01_gpio_block_1 is
```

The unique_id (in this example it is changed to ‘2’)

unique_id       : std_logic_vector(31 downto 0) := "00000000000000000000000000000010"

The name of the entity at the end of the entity declaration
```
end entity test01_gpio_block_1;
```
The name of the architecture at the beginning of the architecture declaration
```
architecture rtl of test01_gpio_block_1 is
```

The unique_id at the unique_id_check (in this example it is changed to ‘2’)

unique_id_check : if unique_id /= "00000000000000000000000000000010" generate

The name of the component at the start of the component declaration:
```
 gpio_block_0  component avalon_gpio_interface
```
The unique_id in the generic map of the component decleration (in this example it is changed to ‘2’)
```
unique_id       => "00000000000000000000000000000010"
```

3.) Modify the *.qib-file

At approximately line 10 add a new line for each copy created in the last step. The name and the number of the block have to be adapted.

set_global_assignment -library "test01" -name VHDL_FILE [file join $::quartus(qip_path) "test01_gpio_block_1.vhd"]

4.) Modify the main *.vhd-file

The main *.vhd-file has the same name as the Qsys. For example: system.test01.vhd
Search for the component declaration of your template(s)
Make a copy of the declaration for each copy made in step 2
Modify the names of the new declarations (first and last line of the declaration):

	component test01_gpio_block_1 is

		--... shortened ... 
		
	end component test01_gpio_block_1;

Find the port map for all blocks which belong to the new created components

gpio_block_1 : component test01_gpio_block_0

Adapt the component names

gpio_block_1 : component test01_gpio_block_1

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