Universal Serial Interface to FPGA's https://flink-project.ch/ 2026-04-28T19:21:54+00:00 https://flink-project.ch/ https://flink-project.ch/_media/wiki/dokuwiki.svg text/html 2024-08-07T13:05:59+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/start?rev=1723035959&do=diff flink, Universal Interface to FPGA's Downloads * flink on Github flink is .. * an universal serial interface to FPGA's * a collection of useful blocks in a FPGA * open-source * highly flexible * real-time capable flink can be read as fast link or as the German text/html 2024-06-13T11:49:04+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/flink_lib?rev=1718279344&do=diff flink Userspace Library Downloads * flink Userspace Library on Github This is the user documentation for the flink userspace library in C. It provides a device and bus independent interface to the underlying driver modules. For more information about the inner workings see flink Userspace Library on Github. The text/html 2024-04-09T18:46:24+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/subdevices?rev=1712688384&do=diff Available Subdevices The functions given below have so far been implemented as VHDL modules (see flinkVHDL). For all of them a suitable driver is available in the flink Userspace Library and the flinkLite Library. function idnamedescription0x00Infoinfo subdevice with description0x01AnalogInanalog input, ADC0x02AnalogOutanalog output, DAC0x05DigitalIOdigital input and output, GPIO0x06Countercounter0x0c text/html 2023-12-19T15:10:25+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/flink_linux?rev=1702998625&do=diff flink Linux Kernel Modules Downloads * flink Linux Kernel Modules on Github This is the user documentation for the flink kernel modules. They offer drivers capabilities to communicate with various hardware interfaces. For more information about the inner workings see flink Linux Kernel Modules on Github. The driver API text/html 2023-12-13T08:07:49+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/flink_vhdl?rev=1702454869&do=diff VHDL Downloads * flink VHDL Modules on Github This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. Overview Functions * Available functions We currently support various functions which are implemented in subdevices. More functions will be developed in the near future. text/html 2019-12-13T06:47:07+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=block_design_example.png&ns=0&rev=1576219627&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/block_design_example.png?w=500&amp;h=500&amp;tok=4b3e89" alt="block_design_example.png" loading="lazy" width="500" height="500" /> text/html 2018-01-30T10:08:24+00:00 sfink (sfink@undisclosed.example.com) https://flink-project.ch/?image=infodevice-settings-4subdevices.png&ns=0&rev=1517306904&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/infodevice-settings-4subdevices.png?w=500&amp;h=500&amp;tok=76da23" alt="infodevice-settings-4subdevices.png" loading="lazy" width="500" height="500" /> text/html 2018-01-30T10:08:24+00:00 sfink (sfink@undisclosed.example.com) https://flink-project.ch/?image=address-editor.png&ns=0&rev=1517306904&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/address-editor.png?w=500&amp;h=500&amp;tok=bcf3e4" alt="address-editor.png" loading="lazy" width="500" height="500" /> text/html 2015-03-28T07:13:31+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=lpb_mpc5200b_to_avalon.png&ns=0&rev=1427526811&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/lpb_mpc5200b_to_avalon.png?w=500&amp;h=500&amp;tok=cd0cd5" alt="lpb_mpc5200b_to_avalon.png" loading="lazy" width="500" height="500" /> text/html 2015-03-28T07:13:16+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=lpb_mpc5200io_qsys_sys.png&ns=0&rev=1427526796&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/lpb_mpc5200io_qsys_sys.png?w=500&amp;h=500&amp;tok=44f247" alt="lpb_mpc5200io_qsys_sys.png" loading="lazy" width="500" height="500" /> text/html 2015-03-28T07:13:01+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=lpb_qsys.png&ns=0&rev=1427526781&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/lpb_qsys.png?w=500&amp;h=500&amp;tok=9429b1" alt="lpb_qsys.png" loading="lazy" width="500" height="500" /> text/html 2015-03-28T07:12:54+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=lpb_avalon.png&ns=0&rev=1427526774&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/lpb_avalon.png?w=500&amp;h=500&amp;tok=305a04" alt="lpb_avalon.png" loading="lazy" width="500" height="500" /> text/html 2015-03-28T07:02:43+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=spi_qsys.png&ns=0&rev=1427526163&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/spi_qsys.png?w=500&amp;h=500&amp;tok=ad0cae" alt="spi_qsys.png" loading="lazy" width="500" height="500" /> text/html 2015-03-28T06:52:44+00:00 ursgraf (ursgraf@undisclosed.example.com) https://flink-project.ch/?image=spi_avalon.png&ns=0&rev=1427525564&tab_details=history&media_do=diff&do=media <img src="https://flink-project.ch/_media/spi_avalon.png?w=500&amp;h=500&amp;tok=5c80fd" alt="spi_avalon.png" loading="lazy" width="500" height="500" />