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flink_example_1 [2015/03/28 08:16] – ursgraf | flink_example_1 [2016/02/25 13:32] (current) – external edit 127.0.0.1 | ||
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=== Build into kernel === | === Build into kernel === | ||
- | Compile kernel modules (see [[software: | + | Compile kernel modules (see [[flink_linux|flink Linux Kernel Modules]]) and add them to your kernel image. Add a subnode '' |
=== Load manually === | === Load manually === | ||
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spi_setup(dev); | spi_setup(dev); | ||
</ | </ | ||
- | Finally, compile kernel modules (see [[software: | + | Finally, compile kernel modules (see [[flink_linux|flink Linux Kernel Modules]]), transfer them to the target and load them: |
< | < | ||
insmod flink.ko | insmod flink.ko | ||
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==== flink library and application ==== | ==== flink library and application ==== | ||
- | Compile the flink library (see [[software: | + | Compile the flink library (see [[flink_lib|flink Userspace Library]]) together with several test applications. Transfer the library and the test application to the target. Make sure that your library path includes the actual location of your library. Run test applications such as '' |
===== Onboard FPGA connected through Local Plus Bus ===== | ===== Onboard FPGA connected through Local Plus Bus ===== | ||
=== Setup === | === Setup === | ||
- | * Configure the board with a working Linux kernel and root file system or use the system described in [[software:linux:emdebian:phycore-mpc5200b|Installation von Emdebian Grip auf den Phytec phyCORE-MPC5200B]] | + | * Configure the board with a working Linux kernel and root file system or use the system described in [[http:// |
* Make sure that the device tree blob is up-to-date. It must contain a node for the FPGA sitting on the local plus bus. | * Make sure that the device tree blob is up-to-date. It must contain a node for the FPGA sitting on the local plus bus. | ||
* Get necessary sources for the flink project.< | * Get necessary sources for the flink project.< | ||
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Proceed as described in [[flink_vhdl|flink VHDL]]. | Proceed as described in [[flink_vhdl|flink VHDL]]. | ||
* In 5: add a block //gpio// and a block //pwm// to the system. Also add a // | * In 5: add a block //gpio// and a block //pwm// to the system. Also add a // | ||
- | * In 6: set the '' | + | * In 6: set the '' |
* After 10: the system should now look like: [{{ lpb_qsys.png? | * After 10: the system should now look like: [{{ lpb_qsys.png? | ||
* In 15: assign the pins as follows: | * In 15: assign the pins as follows: |