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flink_example_2 [2018/01/29 22:02] – [FPGA Connection] sfink | flink_example_2 [2019/12/12 21:30] – [Setup FPGA Design] ursgraf | ||
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===== Setup FPGA Design ===== | ===== Setup FPGA Design ===== | ||
- | - Proceed | + | Start as described in [[flink_vhdl|flink VHDL]]. |
- | - For appropriate device choose xc7z010clg400-1. | + | |
- | - For subdevices add a pwmDevice, a gpioDevice and a infoDecice. | + | |
- | - Add default ports by right clicking on the pwm and gpios output port and selecting Create port. Just leave the standard values and press OK. | + | |
- | - For the gpioDevice set the Unique Id to 0x00000001 by double clicking it. | + | |
- | - In the pwmDevices options set the Unique Id to 0x00000002 and the Base Clk to 50000000. | + | |
- | - In the ZYNQ7 block open the Peripherial I/O Pins tab and activate UART 1. | + | |
- | - For the Pin Mapping add the ZYBO_Master.xdc file under Constraints which can be found [[https:// | + | |
- | - Also change line 52 and 53 to set_property PACKAGE_PIN M15 [get_ports {s00_oslv_pwm[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {s00_oslv_pwm[0]}] | + | |
- | - Then right click on the block design in the sources tab and chose Create HDL Wrapper... | + | |
- | - Next create bitstream | + | |
- | - Than export the Hardware. Don't forget to include the Bitstream. | + | |
- | - After that launch the inbuilt SDK | + | |
- | In the end the block diagram should look like this: | + | 2. Under the tab //Boards// select Zybo [[ https:// |
+ | 8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\ | ||
+ | 10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 50000000. \\ | ||
+ | 13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https:// | ||
+ | < | ||
+ | set_property -dict { PACKAGE_PIN B19 | ||
+ | set_property -dict { PACKAGE_PIN B20 | ||
+ | set_property -dict { PACKAGE_PIN A20 | ||
+ | set_property -dict { PACKAGE_PIN E17 | ||
+ | |||
+ | set_property -dict { PACKAGE_PIN T10 | ||
+ | set_property -dict { PACKAGE_PIN U12 | ||
+ | </ | ||
+ | 14. //Dev Size// for our three subdevices together is 12288. | ||
+ | |||
+ | In the end the block diagram should look like this: \\ | ||
+ | (Instead of the " | ||
{{:: | {{:: | ||
+ | |||
===== flinkLite ===== | ===== flinkLite ===== | ||
- | If there is no operating system used on the Zybo, flinkLite can be used to get easyer | + | If there is no operating system used on the Zybo, flinkLite can be used to get easier |
+ | - Create your Bitstream as described above. | ||
+ | - Click on „File“ -> „Export“ -> „Export Hardware“. | ||
+ | - Include your bitstream and click „OK“. | ||
+ | - Launch Xilinx SDK: „File“ -> „Launch SDK“. | ||
+ | - Create a new Application Project: „File“ -> „New“ -> „Application Project“. | ||
+ | - Enter a project name and click „Finish“, | ||
+ | - In the „Project Explorer“ right click on your „src“-folder and add a new folder. | ||
+ | - Click on „Advanced“ and choose „Link to alternate location (Linked Folder). | ||
+ | - Browse to „flinkLite“ -> „flink“ -> „flinklib“ choose „flinklib“ and click „OK“. | ||
+ | - Right click on your project and open the „Properties“. | ||
+ | - Under „C/C++ General“ -> „Paths and Symbols“ add the flinklib folder: „Add“ -> directory = „src/ | ||
+ | - Your project should now rebuild and you are ready to use flink. | ||
- | The first step after starting the SDK is to create a application project with " | ||
- | Than add the flinklight sources to the project by right clicking on the src folder and choose new Folder. Press the Advanced button and check "Link to alternate location" | ||
- | Next we add the newly added folder as include directory.To to that right click on the project and choose Properties. Than go to C/C++ General-> | ||
Next we will have a look at the following example code: | Next we will have a look at the following example code: | ||
Line 101: | Line 115: | ||
The next step is to open the flinkdevice with the flink_open(& | The next step is to open the flinkdevice with the flink_open(& | ||
- | With the flink_get_nof_subdevices(dev) method we can check how many subdevices have been found. In our case this should return 3 (info, pwm, gpio) | + | With the flink_get_nof_subdevices(dev) method we can check how many subdevices have been found. In our case this should return 3 (info, pwm, gpio). If this is not the case, ensure that you have entered the correct value for "Dev Size" in the infoDevice. The correct value is: number of flink subdevices * 4096. |
To easy access the subdevices we need a reverence to them. There are different ways to get this reference. In our example we will use the flink_get_subdevice_by_unique_id(dev, | To easy access the subdevices we need a reverence to them. There are different ways to get this reference. In our example we will use the flink_get_subdevice_by_unique_id(dev, | ||
- | After we have a reference to a subdevice we can use the subdevice specific methods to interact with it. In our example we us three methods to configure the pwm output. First we get the base clock frequency with wich the pwm subdevice is connected. For that we us flink_pwm_get_baseclock(pwm_subdev,& | + | After we have a reference to a subdevice we can use the subdevice specific methods to interact with it. In our example we us three methods to configure the pwm output. First we get the base clock frequency with wich the pwm subdevice is connected. For that we us flink_pwm_get_baseclock(pwm_subdev,& |
- | flink_pwm_set_hightime(pwm_subdev, | + | flink_pwm_set_hightime(pwm_subdev, |
- | The same thing we can do with the gpio subdevice. There we only need two methods: with flink_dio_set_direction(gpio_subdev, | + | The same thing we can do with the gpio subdevice. There we only need two methods: with flink_dio_set_direction(gpio_subdev, |
- | ===== Flink Linux ===== | + | ===== flinkLinux |
The Linux part works the same on all systems please checke [[http:// | The Linux part works the same on all systems please checke [[http:// | ||
+ | ===== Used ressources ===== | ||
+ | All listed modules also include the Zynq7-Processing System, the Processor System Reset and one AXI-Smartconnect. | ||
+ | |**Module**|**LUT**|**FF**| | ||
+ | |infoDevice | 1372| 1188| | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||