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flink_example_2 [2018/01/30 11:51] – [Flink Linux] sfink | flink_example_2 [2019/12/17 15:21] (current) – ursgraf | ||
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===== Setup FPGA Design ===== | ===== Setup FPGA Design ===== | ||
- | - Proceed | + | Start as described in [[flink_vhdl|flink VHDL]]. |
- | - Under the tab " | + | |
- | - For subdevices add a pwmDevice, a gpioDevice and a infoDevice. | + | |
- | - Add default ports by right clicking on the pwm and gpios output port and selecting Create port. Just leave the standard values and press OK. | + | |
- | - For the gpioDevice set the Unique Id to 0x00000001 by double clicking it. | + | |
- | - In the pwmDevices options set the Unique Id to 0x00000002 and the Base Clk to 50000000. | + | |
- | - In the ZYNQ7 block open the Peripherial I/O Pins tab and activate UART 1. | + | |
- | - For the Pin Mapping add the ZYBO_Master.xdc file under Constraints which can be found [[https:// | + | |
- | - Then uncomment and change line 27 to:// | + | |
- | - Also uncomment and change line 28 to:// | + | |
- | - Then right click on the block design in the sources tab and chose Create HDL Wrapper... | + | |
- | - Next create bitstream | + | |
- | - Than export the Hardware. Don't forget to include the Bitstream. | + | |
- | - After that launch the Xilinx-SDK | + | |
- | In the end the block diagram should look like this: | + | 2. Under the tab //Boards// select Zybo [[ https:// |
+ | 8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\ | ||
+ | 10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 100000000 (check how your kernel sets the PL clock). \\ | ||
+ | 13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https:// | ||
+ | < | ||
+ | set_property -dict { PACKAGE_PIN B19 | ||
+ | set_property -dict { PACKAGE_PIN B20 | ||
+ | set_property -dict { PACKAGE_PIN A20 | ||
+ | set_property -dict { PACKAGE_PIN E17 | ||
+ | |||
+ | set_property -dict { PACKAGE_PIN T10 | ||
+ | set_property -dict { PACKAGE_PIN U12 | ||
+ | </ | ||
+ | 14. //Dev Size// for our three subdevices together is 12288. | ||
+ | |||
+ | Finally, | ||
+ | (Instead of the " | ||
{{:: | {{:: | ||
+ | |||
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If there is no operating system used on the Zybo, flinkLite can be used to get easier access to the fpga design. | If there is no operating system used on the Zybo, flinkLite can be used to get easier access to the fpga design. | ||
- | - Create your Bitstream as described | + | - Create your Bitstream as described |
- | - Click on „File“ -> „Export“ -> „Export Hardware“ | + | - Click on „File“ -> „Export“ -> „Export Hardware“. |
- | - Include your bitstream and click „OK“ | + | - Include your bitstream and click „OK“. |
- | - Launch Xilinx SDK: „File“ -> „Launch SDK“ | + | - Launch Xilinx SDK: „File“ -> „Launch SDK“. |
- | - Create a new Application Project: „File“ -> „New“ -> „Application Project“ | + | - Create a new Application Project: „File“ -> „New“ -> „Application Project“. |
- Enter a project name and click „Finish“, | - Enter a project name and click „Finish“, | ||
- In the „Project Explorer“ right click on your „src“-folder and add a new folder. | - In the „Project Explorer“ right click on your „src“-folder and add a new folder. | ||
- Click on „Advanced“ and choose „Link to alternate location (Linked Folder). | - Click on „Advanced“ and choose „Link to alternate location (Linked Folder). | ||
- | - Browse to „flinkLite“ -> „flink“ -> „flinklib“ choose „flinklib“ and click „OK“ | + | - Browse to „flinkLite“ -> „flink“ -> „flinklib“ choose „flinklib“ and click „OK“. |
- | - Right click on your project and open the „Properties“ | + | - Right click on your project and open the „Properties“. |
- | - Under „C/C++ General“ -> „Paths and Symbols“ add the flinklib folder: „Add“ -> directory = „src/ | + | - Under „C/C++ General“ -> „Paths and Symbols“ add the flinklib folder: „Add“ -> directory = „src/ |
- Your project should now rebuild and you are ready to use flink. | - Your project should now rebuild and you are ready to use flink. | ||
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The Linux part works the same on all systems please checke [[http:// | The Linux part works the same on all systems please checke [[http:// | ||
+ | ===== Used ressources ===== | ||
+ | All listed modules also include the Zynq7-Processing System, the Processor System Reset and one AXI-Smartconnect. | ||
+ | |**Module**|**LUT**|**FF**| | ||
+ | |infoDevice | 1372| 1188| | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||
+ | |infoDevice, | ||