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flink_example_2 [2019/12/12 20:54] – ursgraf | flink_example_2 [2019/12/12 21:30] – [Setup FPGA Design] ursgraf | ||
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Start as described in [[flink_vhdl|flink VHDL]]. Follow below directions at the specific step. | Start as described in [[flink_vhdl|flink VHDL]]. Follow below directions at the specific step. | ||
- | 2. Under the tab //Boards// select Zybo. [[ https:// | + | 2. Under the tab //Boards// select Zybo [[ https:// |
- | 8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. | + | 8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. |
- | + | 10. Set Unique Id of the gpioDevice | |
- | - Add default ports by right clicking on the pwm and gpios output port and selecting Create port. Just leave the standard values and press OK. | + | 13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https:// |
- | - For the gpioDevice set the Unique Id to 0x00000001 | + | < |
- | - In the pwmDevices options | + | set_property -dict { PACKAGE_PIN |
- | - In the ZYNQ7 block open the Peripherial I/O Pins tab and activate UART 1. | + | set_property |
- | - For the Pin Mapping add the ZYBO_Master.xdc file under Constraints which can be found [[https:// | + | set_property -dict { PACKAGE_PIN |
- | - Then uncomment and change line 27 to: //set_property -dict { PACKAGE_PIN | + | set_property -dict { PACKAGE_PIN E17 |
- | - Also uncomment and change line 28 to: //set_property -dict { PACKAGE_PIN | + | |
- | - Then right click on the block design in the sources tab and chose Create HDL Wrapper... | + | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { s00_oslv_pwm[0] }]; |
- | - Finally create bitstream | + | set_property |
+ | </ | ||
+ | 14. //Dev Size// for our three subdevices together is 12288. | ||
In the end the block diagram should look like this: \\ | In the end the block diagram should look like this: \\ |