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flink_example_2 [2019/12/12 21:12] – ursgraf | flink_example_2 [2019/12/12 21:28] – [Setup FPGA Design] ursgraf | ||
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2. Under the tab //Boards// select Zybo [[ https:// | 2. Under the tab //Boards// select Zybo [[ https:// | ||
8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\ | 8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\ | ||
- | 10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 50000000. | + | 10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 50000000. |
- | 13. For the pin mapping | + | 13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https:// |
+ | < | ||
+ | set_property -dict { PACKAGE_PIN B19 | ||
+ | set_property -dict { PACKAGE_PIN B20 | ||
+ | set_property -dict { PACKAGE_PIN A20 | ||
+ | set_property -dict { PACKAGE_PIN E17 | ||
+ | |||
+ | set_property -dict { PACKAGE_PIN T10 | ||
+ | set_property -dict { PACKAGE_PIN U12 | ||
+ | </ | ||
+ | 14. //Dev Size// for our three subdevices together is 12288. | ||
| | ||
- | - | ||
- | - Then uncomment and change line 27 to: // | ||
- | - Also uncomment and change line 28 to: // | ||
- Then right click on the block design in the sources tab and chose Create HDL Wrapper... | - Then right click on the block design in the sources tab and chose Create HDL Wrapper... | ||
- Finally create bitstream | - Finally create bitstream |