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flink_example_2 [2019/12/12 21:22] – [Setup FPGA Design] ursgraf | flink_example_2 [2019/12/12 21:30] – [Setup FPGA Design] ursgraf | ||
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set_property -dict { PACKAGE_PIN U12 | set_property -dict { PACKAGE_PIN U12 | ||
</ | </ | ||
- | + | 14. //Dev Size// for our three subdevices together is 12288. | |
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- | - | + | |
- | - Then uncomment and change line 27 to: //set_property -dict { PACKAGE_PIN M14 | + | |
- | - Also uncomment and change line 28 to: // | + | |
- | - Then right click on the block design in the sources tab and chose Create HDL Wrapper... | + | |
- | - Finally create bitstream | + | |
In the end the block diagram should look like this: \\ | In the end the block diagram should look like this: \\ |