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flink_example_2 [2019/12/12 21:30] – [Setup FPGA Design] ursgraf | flink_example_2 [2019/12/13 07:47] – [Setup FPGA Design] ursgraf | ||
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14. //Dev Size// for our three subdevices together is 12288. | 14. //Dev Size// for our three subdevices together is 12288. | ||
- | In the end the block diagram should look like this: \\ | + | Finally, |
(Instead of the " | (Instead of the " | ||