User Tools
flink_example_2
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
flink_example_2 [2018/02/04 11:03] sfink [Setup FPGA Design] |
flink_example_2 [2019/12/17 15:21] (current) ursgraf |
||
|---|---|---|---|
| Line 6: | Line 6: | ||
| ===== Setup FPGA Design ===== | ===== Setup FPGA Design ===== | ||
| - | - Proceed as described in [[flink_vhdl|flink VHDL]]. | + | Start as described in [[flink_vhdl|flink VHDL]]. Follow below directions at the specific step. |
| - | - Under the tab "Boards" select Zybo. [[ https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 | Add Zybo to Boards]] | + | |
| - | - For subdevices add a pwmDevice, a gpioDevice and a infoDevice. | + | |
| - | - Add default ports by right clicking on the pwm and gpios output port and selecting Create port. Just leave the standard values and press OK. | + | |
| - | - For the gpioDevice set the Unique Id to 0x00000001 by double clicking it. | + | |
| - | - In the pwmDevices options set the Unique Id to 0x00000002 and the Base Clk to 50000000. | + | |
| - | - In the ZYNQ7 block open the Peripherial I/O Pins tab and activate UART 1. | + | |
| - | - For the Pin Mapping add the ZYBO_Master.xdc file under Constraints which can be found [[https://reference.digilentinc.com/zybo/zybo | here]]. | + | |
| - | - Then uncomment and change line 27 to: //set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { oslv_gpios[0] }];// | + | |
| - | - Also uncomment and change line 28 to: //set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { s00_oslv_pwm[0] }];// | + | |
| - | - Then right click on the block design in the sources tab and chose Create HDL Wrapper... | + | |
| - | - Finally create bitstream | + | |
| + | 2. Under the tab //Boards// select Zybo [[ https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 | Add Zybo to Boards]]. \\ | ||
| + | 8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\ | ||
| + | 10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 100000000 (check how your kernel sets the PL clock). \\ | ||
| + | 13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https://reference.digilentinc.com/zybo/zybo | here]]. | ||
| + | <code> | ||
| + | set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { oslv_gpios[0] }]; | ||
| + | set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { oslv_gpios[1] }]; | ||
| + | set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { oslv_gpios[2] }]; | ||
| + | set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { oslv_gpios[3] }]; | ||
| + | |||
| + | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { s00_oslv_pwm[0] }]; | ||
| + | set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { s00_oslv_pwm[1] }]; | ||
| + | </code> | ||
| + | 14. //Dev Size// for our three subdevices together is 12288. | ||
| - | In the end the block diagram should look like this: \\ | + | Finally, the block diagram should look like: \\ |
| (Instead of the "AXI-Interconnect" IP in the middle, it is also possible to use a "AXI-Smartconnect" IP.) | (Instead of the "AXI-Interconnect" IP in the middle, it is also possible to use a "AXI-Smartconnect" IP.) | ||
flink_example_2.1517738582.txt.gz · Last modified: 2018/02/04 11:03 by sfink
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 4.0 International
