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flink_example_2
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flink_example_2 [2018/02/04 11:02] sfink [Setup FPGA Design] |
flink_example_2 [2018/02/04 11:03] (current) sfink [Setup FPGA Design] |
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| - | In the end the block diagram should look like this: | + | In the end the block diagram should look like this: \\ |
| - | Instead of the "AXI-Interconnect" IP in the middle, it is also possible to use a "AXI-Smartconnect" IP. | + | (Instead of the "AXI-Interconnect" IP in the middle, it is also possible to use a "AXI-Smartconnect" IP.) |
| {{::block_design_example.png?1000|}} | {{::block_design_example.png?1000|}} | ||
flink_example_2.txt · Last modified: 2018/02/04 11:03 by sfink
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