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Universal Serial Interface to FPGA's

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flink_example_2

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flink_example_2 [2019/12/12 21:22] – [Setup FPGA Design] ursgrafflink_example_2 [2019/12/17 15:21] (current) – ursgraf
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  2. Under the tab //Boards// select Zybo [[ https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 | Add Zybo to Boards]]. \\  2. Under the tab //Boards// select Zybo [[ https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 | Add Zybo to Boards]]. \\
  8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\  8. The example shown below uses a pwmDevice, a gpioDevice, and an infoDevice. \\
-10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 50000000. \\+10. Set Unique Id of the gpioDevice to 0x00000001, set Unique Id of the pwmDevices to 0x00000002 and the Base Clk to 100000000 (check how your kernel sets the PL clock). \\
 13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https://reference.digilentinc.com/zybo/zybo | here]].  13. Add a constraints file for the pin mapping. The ZYBO_Master.xdc file can be found [[https://reference.digilentinc.com/zybo/zybo | here]]. 
 <code> <code>
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 set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { s00_oslv_pwm[1] }];  set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { s00_oslv_pwm[1] }]; 
 </code> </code>
 +14. //Dev Size// for our three subdevices together is 12288.
  
- +Finally, the block diagram should look like: \\
-   +
-  - Then right click on the block design in the sources tab and chose Create HDL Wrapper...  +
-  - Finally create bitstream +
- +
- +
-In the end the block diagram should look like this: \\+
 (Instead of the "AXI-Interconnect" IP in the middle, it is also possible to use a "AXI-Smartconnect" IP.) (Instead of the "AXI-Interconnect" IP in the middle, it is also possible to use a "AXI-Smartconnect" IP.)
  
flink_example_2.1576182177.txt.gz · Last modified: 2019/12/12 21:22 by ursgraf

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