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flink_first_steps [2015/03/27 17:12] – [FPGA Side] ursgraf | flink_first_steps [2018/01/30 11:50] (current) – [FPGA Side] sfink | ||
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The VHDL modules can be found in [[flink_vhdl|flink VHDL]]. The blue boxes denote automatically created files. The red boxes symbolise planned components which are not yet available. For the time being you have to manually configure your VHDL project. \\ | The VHDL modules can be found in [[flink_vhdl|flink VHDL]]. The blue boxes denote automatically created files. The red boxes symbolise planned components which are not yet available. For the time being you have to manually configure your VHDL project. \\ | ||
- | Currently we only support Altera | + | Currently we support Altera |
===== Processor Side ===== | ===== Processor Side ===== | ||
- | The processor will be connected to the FPGA through a certain interface. On a Linux system suitable kernel modules enable this communication (see [[software: | + | The processor will be connected to the FPGA through a certain interface. On a Linux system suitable kernel modules enable this communication (see [[flink_linux|flink Linux Kernel Modules]]). You can write your application in user space using the API offered by the [[flink_lib|flink Userspace Library]]. The figure below shows the workflow. |
- | [{{ ..:flink: | + | [{{ ..: |
Here again, blue boxes denote automatically created files. | Here again, blue boxes denote automatically created files. | ||