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flink_vhdl [2018/01/29 21:57] – sfink | flink_vhdl [2018/01/30 11:11] – [Building] sfink | ||
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- In the "IP INTEGRATOR" | - In the "IP INTEGRATOR" | ||
- Add a ZYNQ7 Processor System to the design and click "Run Block Automation" | - Add a ZYNQ7 Processor System to the design and click "Run Block Automation" | ||
+ | - Double click the Processor System. In the "clock configuration" | ||
- Open the IP Catalog(blue cross) and add all needed subdevices found under User Repository-> | - Open the IP Catalog(blue cross) and add all needed subdevices found under User Repository-> | ||
- In the Block Design press "Run Connection Automation" | - In the Block Design press "Run Connection Automation" | ||
- Right click on the ports of the subdevices and create ports nesessary. | - Right click on the ports of the subdevices and create ports nesessary. | ||
- | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. If an infoDevice is used make sure it is on the first memory address. | + | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. If an infoDevice is used make sure it is on the first memory address. |
- Add pin mapping. For specific boards you can get your .xdc-files [[https:// | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// | ||
- Ensure that every fLink Subdevice has its own unique id. | - Ensure that every fLink Subdevice has its own unique id. | ||
- | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096. | + | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096.[{{ : |
- Right click on your Block Design and select " | - Right click on your Block Design and select " | ||
- Under „PROGRAM AND DEBUG“ select „Generate Bitstream“. | - Under „PROGRAM AND DEBUG“ select „Generate Bitstream“. |