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flink_vhdl [2019/12/12 21:35] – [Building] ursgraf | flink_vhdl [2019/12/12 21:36] – [Building] ursgraf | ||
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- Right click on your block design and select //Create HDL Wrapper// with //let Vivado manage ...//. | - Right click on your block design and select //Create HDL Wrapper// with //let Vivado manage ...//. | ||
- Under //PROGRAM AND DEBUG// select //Generate Bitstream// | - Under //PROGRAM AND DEBUG// select //Generate Bitstream// | ||
- | - The resulting FPGA configuration file can be found under // | + | - The resulting FPGA configuration file can be found under // |