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flink_vhdl [2020/01/27 16:20] – [Building] ursgraf | flink_vhdl [2020/05/28 10:11] – [VHDL] ursgraf | ||
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====== VHDL ====== | ====== VHDL ====== | ||
<box blue right 38% | **Downloads**> | <box blue right 38% | **Downloads**> | ||
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- | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
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