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flink_vhdl [2020/05/28 10:11] – [VHDL] ursgraf | flink_vhdl [2021/02/04 21:37] – [Building] ursgraf | ||
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* Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices | * Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices | ||
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Vivado (Tested with Version 2016.1, 2017.3 | + | * Vivado (Tested with Version 2016.1, 2017.3, 2017.4 |
===== Id and Unique_Id ===== | ===== Id and Unique_Id ===== | ||
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- In the //IP INTEGRATOR// | - In the //IP INTEGRATOR// | ||
- Add a ZYNQ7 processor system to the design and click //Run Block Automation// | - Add a ZYNQ7 processor system to the design and click //Run Block Automation// | ||
- | - Double click on the processor system. In the //clock configuration// | + | - Double click on the processor system. In the //clock configuration// |
- Add all desired subdevices. Add an //AXI Interconnect// | - Add all desired subdevices. Add an //AXI Interconnect// | ||
- Press //Run Connection Automation// | - Press //Run Connection Automation// |