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flink_vhdl
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flink_vhdl [2018/01/30 11:11] sfink [Building] |
flink_vhdl [2020/05/28 10:11] (current) ursgraf [VHDL] |
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| ====== VHDL ====== | ====== VHDL ====== | ||
| <box blue right 38% | **Downloads**> | <box blue right 38% | **Downloads**> | ||
| - | * [[https://github.com/flink-project/flinkvhdl | fLink VHDL Modules on Github]] | + | * [[https://github.com/flink-project/flinkvhdl | flink VHDL Modules on Github]] |
| </box> | </box> | ||
| - | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
| \\ | \\ | ||
| \\ | \\ | ||
| Line 18: | Line 18: | ||
| * [[.:Multiple subdevices with the same number of ports]] | * [[.:Multiple subdevices with the same number of ports]] | ||
| </box> | </box> | ||
| - | * Quartus Version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 | + | * Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices |
| * Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
| - | * Instead of Altera Quartus, Xilinx Vivado can be used. (Tested with Version 2016.1, 2017.3 and 2017.4) | + | * Vivado (Tested with Version 2016.1, 2017.3 and 2017.4) for Xilinx devices |
| + | |||
| + | ===== Id and Unique_Id ===== | ||
| + | Every subdevice has a parameter ''unique_id''. The user can assign any unique value to it. Please keep a list with these values.\\ | ||
| + | When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the ''id''. A subdevice can now be selected either by its ''unique_id'' or its ''id''. \\ | ||
| + | The ''unique_id'' is defined as a parameter when configuring the subdevice in the FPGA. On the other side, ''id'' is set at runtime when subdevices are scanned. ''id'' therefore depends on the arrangement of the subdevices in a device. ''unique_id'' can be kept constant in any arrangement. \\ | ||
| + | An userland application should use ''unique_id'' when searching for a subdevice. This ensures that the application doesn't have to be recompiled when more subdevices are added to a FPGA design and the memory arrangement changes. | ||
| + | |||
| + | ===== Info Subdevice ===== | ||
| + | An info subdevice serves for information purposes only. It comprises the fields ''unique_id'', ''description'' and ''dev_size'' and has no channels. It can be included in any design if desired. ''dev_size'' is very handy if the interface to the FPGA doesn't allow for enumeration. In those cases the info subdevice can be queried for this field. | ||
| + | \\ | ||
| + | The field ''description'' can be used to ascertain that a specific design is present in the FPGA. | ||
| + | |||
| ===== Building ===== | ===== Building ===== | ||
| ==== Quartus ==== | ==== Quartus ==== | ||
| Line 40: | Line 53: | ||
| - Compile the design and download it. | - Compile the design and download it. | ||
| ==== Vivado ==== | ==== Vivado ==== | ||
| - | - Start Vivado and create a new project. | + | - Start Vivado and create a new project (RTL). |
| - | - Choose your appropriate device. If you want a specific board as target, you can choose it from the tab "Boards". If your board is not listed, you can download the Xilinx-Boards [[https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 | here]]. | + | - Choose your appropriate part. If you want a specific board as target, you can choose it from the tab //Boards//. If your board is not listed, you can download the Xilinx-Boards [[https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 | here]]. |
| - | - Under „Project Manager“ -> „Settings“ in the „General“ tab change target language to VHDL. | + | - Under //Project Manager// -> //Settings// -> //General// change target language to VHDL. |
| - | - Under „IP“ -> „Repository“ add the flinkvhdl root directory with the (green) blue cross. | + | - Under //Project Manager// -> //Settings// -> //IP// -> //Repository// add the flinkvhdl root directory. |
| - | - In the "IP INTEGRATOR" click "create a new Block Design". | + | - In the //IP INTEGRATOR// click //Create Block Design//. |
| - | - Add a ZYNQ7 Processor System to the design and click "Run Block Automation". | + | - Add a ZYNQ7 processor system to the design and click //Run Block Automation//. |
| - | - Double click the Processor System. In the "clock configuration" -> "PL fabric clocks" you can choose the frequency driving the AXI Interface. You should also enter this value in your flink subdevices as baseclock. | + | - Double click on the processor system. In the //clock configuration// -> //PL fabric clocks// you can choose the frequency driving the AXI Interface. You should also later enter this value in your flink subdevices as baseclock. |
| - | - Open the IP Catalog(blue cross) and add all needed subdevices found under User Repository->fLink->Subdevices to the design. | + | - Add all desired subdevices. Add an //AXI Interconnect// device as well. |
| - | - In the Block Design press "Run Connection Automation" -> add all Subdevices | + | - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// the process will automatically add an //AXI SmartConnect//, which does not work with our components. |
| - | - Right click on the ports of the subdevices and create ports nesessary. | + | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. |
| - | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. If an infoDevice is used make sure it is on the first memory address. [{{ ::address-editor.png?400 | Range and address offset of flink devices}}] | + | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type //xilinx.com:interface:gpio_rtl//. |
| + | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | ||
| - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]]. | - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]]. | ||
| - | - Ensure that every fLink Subdevice has its own unique id. | + | - Change the properties of the infoDevice as follows: //Dev Size// must be the total size of all subdevices combined. Set the description to a meaningful name. |
| - | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096.[{{ :infodevice-settings-4subdevices.png?200 | "Dev Size" of an infoDevice with 4 flink subdevices}}] | + | - Right click on your block design and select //Create HDL Wrapper// with //let Vivado manage ...//. |
| - | - Right click on your Block Design and select "Create HDL Wrapper". | + | - Under //PROGRAM AND DEBUG// select //Generate Bitstream//. |
| - | - Under „PROGRAM AND DEBUG“ select „Generate Bitstream“. | + | - The resulting FPGA configuration file can be found under //project_name/project_name/runs/impl_1//. |
| - | ===== Id and Unique_Id ===== | ||
| - | Every subdevice has a parameter ''unique_id''. The user can assign any unique value to it. Please keep a list with these values.\\ | ||
| - | When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the ''id''. A subdevice can now be selected either by its ''unique_id'' or its ''id''. \\ | ||
| - | The ''unique_id'' is defined as a parameter when configuring the subdevice in the FPGA. On the other side, ''id'' is set at runtime when subdevices are scanned. ''id'' therefore depends on the arrangement of the subdevices in a device. ''unique_id'' can be kept constant in any arrangement. \\ | ||
| - | An userland application should use ''unique_id'' when searching for a subdevice. This ensures that the application doesn't have to be recompiled when more subdevices are added to a FPGA design and the memory arrangement changes. | ||
| - | |||
| - | ===== Info Subdevice ===== | ||
| - | An info subdevice serves for information purposes only. It comprises the fields ''unique_id'', ''description'' and ''dev_size'' and has no channels. It can be included in any design if desired. ''dev_size'' is very handy if the interface to the FPGA doesn't allow for enumeration. In those cases the info subdevice can be queried for this field. | ||
| - | \\ | ||
| - | The field ''description'' can be used to assertain that a specific design is present in the FPGA. | ||
| - | |||
flink_vhdl.1517307090.txt.gz · Last modified: 2018/01/30 11:11 by sfink
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