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--- start [2015/02/09 15:30] – external edit 127.0.0.1
+++ start [2024/08/07 15:05] (current) – ursgraf
@@ Line 1: / Line 1: @@
-====== flink, Universal Serial Interface to FPGA's ======
+====== flink, Universal Interface to FPGA's ======
 <box blue right 38% | **Downloads**>
@@ Line 6: / Line 6: @@
 flink is ..
   * an universal serial interface to FPGA's
-  * is open-source
+  * a collection of useful blocks in a FPGA
-  * is highly flexibel
+  * open-source
-  * is real-time capable
+  * highly flexible
+  * real-time capable
-flink can be read as //fast link// or as the German "flink" meaning fast. It enables any processors to communicate with an external FPGA over a serial interface, e.g. PCI or SPI. The FPGA may contain several blocks such as counters or pulse-width modulation. Such blocks are extensively used in robotics for control applications.
+flink can be read as //fast link// or as the German "flink" meaning fast. It enables any processors to communicate with an external FPGA over a parallel interface (e.g. PCI, EIM, LPB, AXI) or serial interface (e.g. SPI). The FPGA may contain several blocks such as counters or pulse-width modulation. Such blocks are extensively used in robotics for control applications. \\
+flink was developed at and is maintained by the Institute of Computer Science at [[http://www.ost.ch|OST]].
 ===== Overview =====
 <box green right 38% | **flink Modules**>
-  * [[.:flink:flink_vhdl|flink VHDL subdevices and interfaces]]
+  * [[.:flink_vhdl|flink VHDL subdevices and interfaces]]
-  * [[.:flink:flink_linux|flink Linux Kernel Modules]]
+  * [[.:flink_linux|flink Linux Kernel Modules]]
-  * [[.:flink:flink_lib|flink Userspace Library]]
+  * [[.:flink_lib|flink Userspace Library]]
-  * [[.:flink:flink_liblite|flink Userspace Library Lite]]
+  * [[.:flink_liblite|flink Userspace Library Lite]]
-  * [[.:flink:flink_utils|flink Utilities]]
+  * [[.:flink_utils|flink Utilities]]
-  * [[.:flink:flink_deep|flink Java Library]]
+  * [[.:flink_python|flink Python Wrapper]]
+  * [[.:flink_deep|flink Java Library]]
 </box>
@@ Line 27: / Line 30: @@
   * flinkLinux: Kernel Modules
   * flinkLib: Userspace library for C/C++
-  * flinkLibLite: Userspace library for OS-less systems for C/C++
+  * flinkLite: Userspace library for OS-less systems for C/C++
   * flinkUtils: Utilities and test programs for the flink library
+  * flinkPython: Python wrapper
   * flinkDeep: Library for Java
-=== Typical use with C/C++ under an operating system ===
+==== Typical use with C/C++ under an operating system ====
 <box red right 38% | **First Steps and Examples**>
-  * [[.:flink:flink_first_steps|flink First Steps]]
+  * [[flink_first_steps|flink First Steps]]
-  * [[.:flink:flink_example_0|flink on a Intel Atom SOC]]
+  * [[flink_example_1|flink on a Phytec PCM032 Board]]
-  * [[.:flink:flink_example_1|flink on a Phytec PCM032 Board]]
+  * [[flink_example_2|flink on a Digilent ZYBO]]
 </box>
-Implement all necessary hardware modules with [[.:flink:flink_vhdl|flink VHDL modules and interfaces]] and choose a suitable interconnection with the available [[.:flink:flink_linux|flink Linux Kernel Modules]]. Develop your application using the [[.:flink:flink_lib|flink Userspace Library]]. The following picture shows the system setup.
+Implement all necessary hardware modules with [[flink_vhdl|flink VHDL modules and interfaces]] and choose a suitable interconnection with the available [[flink_linux|flink Linux Kernel Modules]]. Develop your application using the [[flink_lib|flink Userspace Library]]. The following picture shows the system setup.
-[{{ .:flink:flinkoverviewlinux.png?500 | //flink with OS and C/C++ programming//}}]
+[{{ flinkoverviewlinux.png?500 | //flink with OS and C/C++ programming//}}]
 ===== System Architecture =====
@@ Line 47: / Line 51: @@
   * **channel**: Single channel of a subdevice, corresponds to a single pin of a ''digital IO'' subdevice.
-[{{ .:flink:systemarchitectureexample.png?700 | //System architecture for an example system with a motor drive. The drive controlled by an analog output signal. The motor position is determined with a counter module. //}}]
+[{{ systemarchitectureexample.png?600 | //System architecture for an example system with a motor drive. The drive controlled by an analog output signal. The motor position is determined with a counter module. //}}]
 ===== Memory Mapping =====
@@ Line 62: / Line 66: @@
 |  function id  ||||||||||||||||
 |15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
-|  subfunction id  ||||||||  function version  ||||||||
+|  subtype id  ||||||||  interface version  ||||||||
-All the available functions can be found in [[.:flink:subdevices|Available Subdevices]]. Next comes a subheader. It contains a configuration and status register. The meaning of the single bits of this register can vary according to the function of the subdevice.
+All the available functions can be found in [[subdevices|Available Subdevices]]. Next comes a subheader. It contains a configuration and status register. The meaning of the single bits of these registers can vary according to the function of the subdevice.
 ^Offset^Size [byte] ^Name^r/w^Const^Description^
@@ Line 72: / Line 76: @@
 |0x1c|4| | | |reserved|
-Header and subheader is followed by a subdevice specific part. The content varies according to the function and is listed in [[.:flink:subdevices|Available Subdevices]]
+Header and subheader is followed by a subdevice specific part. The content varies according to the function and is listed in [[subdevices|Available Subdevices]]

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