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subdevices [2015/11/09 17:12] – [GPIO] ursgraf | subdevices [2023/12/19 12:57] – [DAC] ursgraf | ||
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====== Available Subdevices ====== | ====== Available Subdevices ====== | ||
- | The functions given below have so far been implemented as VHDL modules (see [[flink_vhdl|VHDL]]). For all of them a suitable driver is available in the [[flink_lib|flink Userspace Library]] | + | The functions given below have so far been implemented as VHDL modules (see [[flink_vhdl|flinkVHDL]]). For all of them a suitable driver is available in the [[flink_lib|flink Userspace Library]] |
^function id^name^description^ | ^function id^name^description^ | ||
- | |0x00|Info|info subdevice with description| | + | |0x00|Info|[[subdevices# |
- | |0x01|AnalogIn|analog input, ADC| | + | |0x01|AnalogIn|[[subdevices# |
- | |0x02|AnalogOut|analog output, DAC| | + | |0x02|AnalogOut|[[subdevices# |
- | |0x05|DigitalIO|digital input and output, GPIO| | + | |0x05|DigitalIO|[[subdevices# |
- | |0x06|Counter|counter| | + | |0x06|Counter|[[subdevices# |
- | |0x0c|PWM|pulse width modulated output| | + | |0x0c|PWM|[[subdevices# |
- | |0x0d|PPWA|period and pulse width measurement| | + | |0x0d|PPWA|[[subdevices# |
- | |0x10|Watchdog|watchdog timer| | + | |0x0f|UART|[[subdevices# |
- | |0x11|Sensor|various sensors (inductive, acceleration)| | + | |0x10|Watchdog|[[subdevices# |
+ | |0x11|Sensor|[[subdevices# | ||
+ | |0x15|Stepper Motor|[[subdevices# | ||
+ | |0x18|IRQ Muliplexer|[[subdevices# | ||
===== Subdevice Specific Registers ===== | ===== Subdevice Specific Registers ===== | ||
Line 21: | Line 24: | ||
|0x20|4|memory size|r|yes|total memory size for the device (in bytes) including all subdevices| | |0x20|4|memory size|r|yes|total memory size for the device (in bytes) including all subdevices| | ||
|0x24|28|description|r|yes|contains a description, | |0x24|28|description|r|yes|contains a description, | ||
+ | Insert the description in hexadecimal notation, e.g. " | ||
The status and configuration registers in the subheader are unused with this function. | The status and configuration registers in the subheader are unused with this function. | ||
===== ADC ===== | ===== ADC ===== | ||
- | This function is used to gather analog input data from an ADC. | + | This function is used to gather analog input data from an ADC. The ADC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
Line 30: | Line 34: | ||
|0x28|4|value_1|r|no|channel 1: digitized input value| | |0x28|4|value_1|r|no|channel 1: digitized input value| | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses 3 to 4 pins for the SPI depending on the particular type. |
==== Subtypes ==== | ==== Subtypes ==== | ||
- | Currently there are two subtypes of this subdevice. The subtype information can be found in the '' | + | Currently there are three subtypes of this subdevice. The subtype information can be found in the '' |
- | ^ID^Description^Example^ | + | ^Subtype |
|0x1|Simple ADC with continuous sampling|ADC128S102| | |0x1|Simple ADC with continuous sampling|ADC128S102| | ||
|0x2|Advanced model with integrated filter and sampling mode selection|AD7606| | |0x2|Advanced model with integrated filter and sampling mode selection|AD7606| | ||
+ | |0x3|Simple ADC, low power|AD7476| | ||
===== DAC ===== | ===== DAC ===== | ||
- | This function serves to drive an DAC. | + | This function serves to drive an DAC. The DAC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
Line 44: | Line 49: | ||
|0x28|4|value_1|r/ | |0x28|4|value_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses 5 pins. |
==== Subtypes ==== | ==== Subtypes ==== | ||
- | Currently there is one subtype of this subdevice. The subtype information can be found in the '' | + | Currently there is one subtype of this subdevice. The subtype information can be found in the '' |
- | ^ID^Description^Example^ | + | ^Subtype |
|0x1|Simple DAC where the outputs are continuously set. All channels are updated at the same time|AD5668| | |0x1|Simple DAC where the outputs are continuously set. All channels are updated at the same time|AD5668| | ||
===== GPIO ===== | ===== GPIO ===== | ||
- | This function realizes digital inputs and outputs. | + | This function realizes digital inputs and outputs. |
+ | Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because debouncing is derived from that clock. | ||
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
- | |0x20|4|dir_0|r/ | + | |0x20|4|base_clk|r|yes|base clock in Hz| |
- | |0x24|4|dir_1|r/ | + | |0x24|4|dir_0|r/ |
+ | |0x28|4|dir_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
|0xyy|4|val_0|r/ | |0xyy|4|val_0|r/ | ||
|0xyy+4|4|val_1|r/ | |0xyy+4|4|val_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xzz|4|irq_debounce_0|r/ | ||
+ | |0xzz+4|4|irq_debounce_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
A value of ' | A value of ' | ||
The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. \\ | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. \\ | ||
- | At powerup all pins will be inputs. | + | At powerup all pins will be inputs. This subdevice uses a pin on the FPGA device for each channel. |
===== Counter ===== | ===== Counter ===== | ||
- | All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. | + | All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. The counter module implements a 16 bit counter, hence, reading the counter value will return only 2 bytes. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|count_0|r|no|counter channel 0| | |0x20|4|count_0|r|no|counter channel 0| | ||
|0x24|4|count_1|r|no|counter channel 1| | |0x24|4|count_1|r|no|counter channel 1| | ||
|..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. |
+ | ==== Subtypes ==== | ||
+ | Currently there is one subtype of this subdevice. The subtype information can be found in the '' | ||
+ | ^Subtype ID^Description^ | ||
+ | |0x0|fast quadrature decoder (using signals A and B)| | ||
===== PWM ===== | ===== PWM ===== | ||
- | Used to output pulse with modulated output signals. | + | Used to output pulse with modulated output signals. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the frequency setting is derived from this clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
- | |0x20|4|base_clk|r|no|base clock in Hz| | + | |0x20|4|base_clk|r|yes|base clock in Hz| |
|0x24|4|ptime_0|r/ | |0x24|4|ptime_0|r/ | ||
|0x28|4|ptime_1|r/ | |0x28|4|ptime_1|r/ | ||
Line 81: | Line 96: | ||
|0xyy+4|4|htime_1|r/ | |0xyy+4|4|htime_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
===== PPWA ===== | ===== PPWA ===== | ||
- | This function realizes period and pulse width measurements. | + | This function realizes period and pulse width measurements. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the time measurement is derived from that clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
- | |0x20|4|base_clk|r|no|base clock in Hz| | + | |0x20|4|base_clk|r|yes|base clock in Hz| |
|0x24|4|ptime_0|r|no|channel 0: period in multiples of base clock| | |0x24|4|ptime_0|r|no|channel 0: period in multiples of base clock| | ||
|0x28|4|ptime_1|r|no|channel 1: period in multiples of base clock| | |0x28|4|ptime_1|r|no|channel 1: period in multiples of base clock| | ||
Line 93: | Line 108: | ||
|0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | |0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | ||
|..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
- | The status register in the subheader is unused with this function. | + | The status register in the subheader is unused with this function. |
+ | |||
+ | ===== UART ===== | ||
+ | This function implements one or more serial communication interfaces. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the baud rate is derived from that clock. | ||
+ | ^Offset^Size [byte] ^Name^r/ | ||
+ | |0x20|4|base_clk|r|yes|base clock in Hz| | ||
+ | |0x24|4|devider_0|rw|no|uart 0: clock divider for baud rate| | ||
+ | |0x28|4|devider_1|rw|no|uart 1: clock divider for baud rate| | ||
+ | |..|4|..|rw|no|..| | ||
+ | |0xyy|4|tx_0|rw|no|uart 0: transmit register| | ||
+ | |0xyy+4|4|tx_1|rw|no|uart 1: transmit register| | ||
+ | |..|4|..|rw|no|..| | ||
+ | |0xzz|4|rx_0|r|no|uart 0: receive register| | ||
+ | |0xzz+4|4|rx_1|r|no|uart 1: receive register| | ||
+ | |..|4|..|r|no|..| | ||
+ | |0xuu|4|stat_0|r|no|uart 0: status register| | ||
+ | |0xuu+4|4|stat_1|r|no|uart 1: status register| | ||
+ | |..|4|..|r|no|..| | ||
+ | Both the transmit and receive path contain a 1024 entry FIFO memory. \\ | ||
+ | The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting | ||
+ | | 31...26 | 25...16 | 15...7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | ||
+ | | unused | number of active entries in rx FIFO |unused|tx FIFO full|tx FIFO half full|tx FIFO empty|unused|rx FIFO full|rx FIFO half full|rx FIFO empty|\\ | ||
+ | This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | ||
===== Watchdog ===== | ===== Watchdog ===== | ||
- | If the counter reaches 0 the watchdog fires and osl_granted goes to ' | + | The watchdog is a decrementing |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|base_clk|r|yes|base clock in Hz| | |0x20|4|base_clk|r|yes|base clock in Hz| | ||
- | |0x24|4|status_conf|r/ | + | |0x24|4|counter|r/ |
- | |0x28|4|counter|r/ | + | |
- | === status_conf === | + | The last bit in the status |
- | | 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | | + | The last bit in the configuration register holds the rearm bit. When the watchdog has fired (timed out), it has to be reset by setting the rearm bit. Write ' |
- | | | | | | | | | |rearm|status| | + | counter: set the watchdog timeout before you arm the watchdog. |
- | status: shows the value of the osl_granted | + | |
- | rearm: When the watchdog has fired, it has to be reset with this signal. Write ' | + | |
+ | === Outputs === | ||
+ | This subdevice uses two pins on the FPGA device. The two output are as follows | ||
+ | * watchdog_pwm: | ||
+ | * granted: outputs logic ' | ||
===== Sensor ===== | ===== Sensor ===== | ||
==== Subtypes ==== | ==== Subtypes ==== | ||
- | Currently there are two subtypes of this subdevice. The subtype information can be found in the '' | + | Currently there are two subtypes of this subdevice. The subtype information can be found in the '' |
^ID^Description^Example^ | ^ID^Description^Example^ | ||
|0x1|Inductance to digital converter|LDC1000| | |0x1|Inductance to digital converter|LDC1000| | ||
|0x2|Motion tracking sensor|LMPU9250| | |0x2|Motion tracking sensor|LMPU9250| | ||
+ | |0x3|Gyroskope|ITG3200| | ||
+ | |0x4|Reflective Photoelectric Sensor|TCRT1000| | ||
==== LDC1000 ==== | ==== LDC1000 ==== | ||
Line 196: | Line 238: | ||
The status and control register in the subheader are described below. | The status and control register in the subheader are described below. | ||
- | === status | + | === Status Register |
| 31 | ... | 05..04 | 03..02 | 01 | 00 | | | 31 | ... | 05..04 | 03..02 | 01 | 00 | | ||
| | | ACCEL_FS_SEL |GYRO_FS_SEL|configuring| reset| | | | | ACCEL_FS_SEL |GYRO_FS_SEL|configuring| reset| | ||
Line 206: | Line 248: | ||
//all other//: All other bits are described in the MPU9250 register map in the manual. | //all other//: All other bits are described in the MPU9250 register map in the manual. | ||
- | === config | + | === Configuration Register |
| 31 | ... | 01 | 00 | | | 31 | ... | 01 | 00 | | ||
| | |update_config|reset| | | | |update_config|reset| | ||
Line 235: | Line 277: | ||
For all data registers only the lower 16 bit are valid. | For all data registers only the lower 16 bit are valid. | ||
+ | |||
+ | ==== ITG3200 ==== | ||
+ | === ITG3200 Specific Registers === | ||
+ | ^Offset^Size [byte] ^Name^r/ | ||
+ | |0x20|4|gyro_xout_h|r|no|GYRO_XOUT_H of the ITG3200| | ||
+ | |0x24|4|gyro_xout_l|r|no|GYRO_XOUT_L of the ITG3200| | ||
+ | |0x28|4|gyro_yout_h|r|no|GYRO_YOUT_H of the ITG3200| | ||
+ | |0x2C|4|gyro_yout_l|r|no|GYRO_YOUT_L of the ITG3200| | ||
+ | |0x30|4|gyro_zout_h|r|no|GYRO_ZOUT_H of the ITG3200| | ||
+ | |0x34|4|gyro_zout_l|r|no|GYRO_ZOUT_L of the ITG3200| | ||
+ | |||
+ | ==== TCRT1000 ==== | ||
+ | This function is used to drive reflective photoelectric sensors of type TRCT1000. Please refer to [[https:// | ||
+ | ^Offset^Size [byte] ^Name^r/ | ||
+ | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
+ | |0x24|4|sensor_0|r|no|channel 0: digitized input value| | ||
+ | |0x28|4|sensor_1|r|no|channel 1: digitized input value| | ||
+ | |..|4|..|r|no|..| | ||
+ | |0xyy|4|irq_level_up_0|r/ | ||
+ | |0xyy+4|4|irq_level_up_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xzz|4|irq_level_low_0|r/ | ||
+ | |0xzz+4|4|irq_level_low_0|r/ | ||
+ | |..|4|..|r/ | ||
+ | |||
+ | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | ||
+ | |||
+ | === Output Signals=== | ||
+ | This subdevice uses three pins to connect an ADC7476. Further, the appropriate number of pins for the decoder is number_of_sensors = 2< | ||
+ | |||
+ | ===== Stepper Motor ===== | ||
+ | Used to control stepper motors. You can set several configuration parameters (forward, backward, full or half step, two or single phase). When starting a motor its speed will ramp up to a given top speed and ramp down to its final position. When in speed mode, a ramp is used to change from its current speed to the new target speed. | ||
+ | |||
+ | Changes in direction, step type, phase mode and start speed are only taking place when the motor is stopped. | ||
+ | Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because prescalers are derived from that clock. | ||
+ | |||
+ | ==== Modes of Operation ==== | ||
+ | === Step Mode === | ||
+ | The motor moves through the specified number of steps. It uses a ramp to accelerate up and down. Changes in the configuration, | ||
+ | |||
+ | === Speed Mode === | ||
+ | The motor ramps up to a preset speed. When the stop command is issued, the speed ramps down to a standstill. Changes in acceleration and starting speed are only applied at standstill. The maximum speed can be changed at will. Any change in maximum speed is reached with a ramp. | ||
+ | |||
+ | === Free Running === | ||
+ | The motor is freewheeling. This means that the windings are not magnetized and the motor has no holding torque. | ||
+ | |||
+ | === General Remarks === | ||
+ | It is not recommended to change from step mode to fix speed mode. It is better to stop the engine first and then change the mode. However, when changing from one of these two modes to free running mode, the motor will simply come to a stop without any braking effect (all windings will be non-magnetized). When resetting the module, the motor keeps the current step (the windings are still magnetized). | ||
+ | |||
+ | ==== Configuration ==== | ||
+ | Setting the bit 0 in the configuration register of the subdevice will reset the steps of all motors. | ||
+ | |||
+ | ^Offset^Size [byte] ^Name^r/ | ||
+ | |0x20|4|base_clk|r|yes|base clock in Hz| | ||
+ | |0x24|4|conf_0|r/ | ||
+ | |0x28|4|conf_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xhh|4|set_conf_0|w|no|motor 0: set bits in conf_0 (atomic)| | ||
+ | |0xhh+4|4|set_conf_1|w|no|motor 1: set bits in conf_0 (atomic)| | ||
+ | |..|4|..|w|no|..| | ||
+ | |0xii|4|reset_conf_0|w|no|motor 0: reset bits in conf_0 (atomic)| | ||
+ | |0xii+4|4|reset_conf_1|w|no|motor 1: reset bits in conf_0 (atomic)| | ||
+ | |..|4|..|w|no|..| | ||
+ | |0xkk|4|start_0|r/ | ||
+ | |0xkk+4|4|start_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xll|4|top_0|r/ | ||
+ | |0xll+4|4|top_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xnn|4|acc_0|r/ | ||
+ | |0xnn+4|4|acc_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xoo|4|dest_steps_0|r/ | ||
+ | |0xoo+4|4|dest_steps_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |0xpp|4|curr_steps_0|r|no|motor 0: current position (number of steps)| | ||
+ | |0xpp+4|4|curr_steps_1|r|no|motor 1: current position (number of steps)| | ||
+ | |..|4|..|r|no|..| | ||
+ | |||
+ | === Motor Configuration Register === | ||
+ | | 31 | ... | 06 | 05 | 04..03 | 02 | 01 | 00 | | ||
+ | | | | Reset Step Counter | Start | Run Mode | Two Phase | Full Step | Direction | | ||
+ | |||
+ | * Direction: 1 => CW; 0=> CCW | ||
+ | * Full Step: 1 => full step; 0=> half step | ||
+ | * Two Phase: 1 => two phase operation, 0 => one phase operation. Only required in full step mode. | ||
+ | * Run Mode: 00 => free running, no holding torque, 01 => stepping mode, 10 => speed mode, 11 => reserved | ||
+ | * Start: if set to 1 the motor will start. Writing a ' | ||
+ | * Reset Step Counter: A ' | ||
+ | |||
+ | The motor configuration register can be reading or writing at address //conf_x//. You can set a given set of bits to ' | ||
+ | |||
+ | === Prescaler === | ||
+ | When a motor is started it will start with its start speed and accelerate to its top speed. Start speed, top speed and acceleration can be configured by setting their corresponding prescaler values. Start and top speed are calculated by the base clock of the submodule divided by the prescaler value. | ||
+ | The acceleration is calculated by the base clock of the submodule divided by 2 times the prescaler value. The acceleration is divided by two within the module because the motor accelerates with each trigger edge. Therefore the LSB is not considered by the acceleration. | ||
+ | |||
+ | === Interrupt === | ||
+ | An interrupt is asserted when the motor reaches its final position. | ||
+ | |||
+ | === Output Signals === | ||
+ | This subdevice uses 4 pins per channel on the FPGA. They are called A, | ||
+ | **Unipolar: | ||
+ | **Bipolar: | ||
+ | |||
+ | ===== Interrupt Multiplexer ===== | ||
+ | Used to connect a large number of IRQ lines coming from flink devices to a limited number of IRQ lines going to the interrupt control hardware of the processor. | ||
+ | |||
+ | ^Offset^Size [byte] ^Name^r/ | ||
+ | |0x20|4|irq_line_0|r/ | ||
+ | |0x24|4|irq_line_1|r/ | ||
+ | |..|4|..|r/ | ||
+ | |||
+ | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | ||
+ | |||
+ | === IRQ Lines === | ||
+ | Each signal of the output vector has a register describing which signal of the input vector to connect to.\\ | ||
+ | 0 => default value\\ | ||
+ | 1 => first signal (LSB) of the input vector.\\ | ||
+ | 2 => second signal of the input vector.\\ | ||
+ | ... | ||