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subdevices [2018/01/30 11:28] – [DAC] sfink | subdevices [2021/01/15 13:13] – [Watchdog] ursgraf | ||
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|0x20|4|memory size|r|yes|total memory size for the device (in bytes) including all subdevices| | |0x20|4|memory size|r|yes|total memory size for the device (in bytes) including all subdevices| | ||
|0x24|28|description|r|yes|contains a description, | |0x24|28|description|r|yes|contains a description, | ||
+ | Insert the description in hexadecimal notation, e.g. " | ||
The status and configuration registers in the subheader are unused with this function. | The status and configuration registers in the subheader are unused with this function. | ||
===== ADC ===== | ===== ADC ===== | ||
- | This function is used to gather analog input data from an ADC. | + | This function is used to gather analog input data from an ADC. The ADC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
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|0x28|4|value_1|r|no|channel 1: digitized input value| | |0x28|4|value_1|r|no|channel 1: digitized input value| | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
==== Subtypes ==== | ==== Subtypes ==== | ||
- | Currently there are two subtypes of this subdevice. The subtype information can be found in the '' | + | Currently there are three subtypes of this subdevice. The subtype information can be found in the '' |
^Subtype ID^Description^Example^ | ^Subtype ID^Description^Example^ | ||
|0x1|Simple ADC with continuous sampling|ADC128S102| | |0x1|Simple ADC with continuous sampling|ADC128S102| | ||
|0x2|Advanced model with integrated filter and sampling mode selection|AD7606| | |0x2|Advanced model with integrated filter and sampling mode selection|AD7606| | ||
+ | |0x3|Simple ADC, low power|AD7476| | ||
===== DAC ===== | ===== DAC ===== | ||
- | This function serves to drive an DAC. | + | This function serves to drive an DAC. The DAC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
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|0x28|4|value_1|r/ | |0x28|4|value_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
==== Subtypes ==== | ==== Subtypes ==== | ||
Currently there is one subtype of this subdevice. The subtype information can be found in the '' | Currently there is one subtype of this subdevice. The subtype information can be found in the '' | ||
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A value of ' | A value of ' | ||
The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. \\ | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. \\ | ||
- | At powerup all pins will be inputs. | + | At powerup all pins will be inputs. This subdevice uses a pin on the FPGA device for each channel. |
===== Counter ===== | ===== Counter ===== | ||
- | All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. | + | All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. The counter module implements a 16 bit counter, hence, reading the counter value will return only 2 bytes. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|count_0|r|no|counter channel 0| | |0x20|4|count_0|r|no|counter channel 0| | ||
|0x24|4|count_1|r|no|counter channel 1| | |0x24|4|count_1|r|no|counter channel 1| | ||
|..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses two pins on the FPGA device for each channel. |
===== PWM ===== | ===== PWM ===== | ||
- | Used to output pulse with modulated output signals. | + | Used to output pulse with modulated output signals. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the frequency setting is derived from this clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|base_clk|r|no|base clock in Hz| | |0x20|4|base_clk|r|no|base clock in Hz| | ||
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|0xyy+4|4|htime_1|r/ | |0xyy+4|4|htime_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
===== PPWA ===== | ===== PPWA ===== | ||
- | This function realizes period and pulse width measurements. | + | This function realizes period and pulse width measurements. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the time measurement is derived from that clock. |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|base_clk|r|no|base clock in Hz| | |0x20|4|base_clk|r|no|base clock in Hz| | ||
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|0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | |0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | ||
|..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
- | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. | + | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
===== Watchdog ===== | ===== Watchdog ===== | ||
- | The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. | + | The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. The field '' |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
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| 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | | | 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | | ||
| | | | | | | | |rearm|status| | | | | | | | | | |rearm|status| | ||
- | status: shows the value of the watchdog signal. If ' | + | status: shows the value of the watchdog signal. If ' |
rearm: When the watchdog has fired (timed out), it has to be reset with this signal. Write ' | rearm: When the watchdog has fired (timed out), it has to be reset with this signal. Write ' | ||
- | counter: before the watchdog | + | counter: |
+ | === Outputs === | ||
+ | This subdevice uses two pins on the FPGA device. The two output are as follows | ||
+ | * watchdog_pwm: | ||
+ | * granted: outputs logic ' | ||
===== Sensor ===== | ===== Sensor ===== |