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subdevices [2020/06/09 16:34] – [GPIO] ursgraf | subdevices [2020/06/09 16:35] – [PPWA] ursgraf | ||
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Line 83: | Line 83: | ||
|0xyy+4|4|htime_1|r/ | |0xyy+4|4|htime_1|r/ | ||
|..|4|..|r/ | |..|4|..|r/ | ||
- | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
===== PPWA ===== | ===== PPWA ===== | ||
Line 95: | Line 95: | ||
|0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | |0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | ||
|..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
- | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. | + | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
===== Watchdog ===== | ===== Watchdog ===== |