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subdevices [2020/06/09 16:35] – [PPWA] ursgraf | subdevices [2021/01/15 16:10] – [Watchdog] ursgraf | ||
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===== Watchdog ===== | ===== Watchdog ===== | ||
- | The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. | + | The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. The field '' |
^Offset^Size [byte] ^Name^r/ | ^Offset^Size [byte] ^Name^r/ | ||
|0x20|4|base_clk|r|yes|base clock in Hz| | |0x20|4|base_clk|r|yes|base clock in Hz| | ||
- | |0x24|4|status_conf|r/ | + | |0x24|4|counter|r/ |
- | |0x28|4|counter|r/ | + | |
- | === status_conf === | + | The last bit in the status |
- | | 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | | + | The last bit in the configuration register holds the rearm bit. When the watchdog has fired (timed out), it has to be reset by setting the rearm bit. Write ' |
- | | | | | | | | | |rearm|status| | + | counter: |
- | status: | + | |
- | rearm: When the watchdog has fired (timed out), it has to be reset with this signal. Write ' | + | |
- | counter: before the watchdog | + | |
=== Outputs === | === Outputs === | ||
+ | This subdevice uses two pins on the FPGA device. The two output are as follows | ||
+ | * watchdog_pwm: | ||
+ | * granted: outputs logic ' | ||
===== Sensor ===== | ===== Sensor ===== |