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subdevices [2021/01/29 12:08] – [UART] ursgraf | subdevices [2021/02/05 08:06] – [UART] ursgraf | ||
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|0xyy+4|4|tx_1|rw|no|uart 1: transmit register| | |0xyy+4|4|tx_1|rw|no|uart 1: transmit register| | ||
|..|4|..|rw|no|..| | |..|4|..|rw|no|..| | ||
- | |0xzz|4|rx_0|rw|no|uart 0: receive register| | + | |0xzz|4|rx_0|r|no|uart 0: receive register| |
- | |0xzz+4|4|rx_1|rw|no|uart 1: receive register| | + | |0xzz+4|4|rx_1|r|no|uart 1: receive register| |
- | |..|4|..|rw|no|..| | + | |..|4|..|r|no|..| |
- | |0xuu|4|stat_0|rw|no|uart 0: status register| | + | |0xuu|4|stat_0|r|no|uart 0: status register| |
- | |0xuu+4|4|stat_1|rw|no|uart 1: status register| | + | |0xuu+4|4|stat_1|r|no|uart 1: status register| |
- | |..|4|..|rw|no|..| | + | |..|4|..|r|no|..| |
- | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | + | Both the transmit and receive path contain a 1024 entry FIFO memory. \\ |
+ | The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. | ||
+ | | 31...26 | 25...16 | 15...7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | ||
+ | | unused | number of active entries in rx FIFO |unused|tx FIFO full|tx FIFO half full|tx FIFO empty|unused|rx FIFO full|rx FIFO half full|rx FIFO empty|\\ | ||
+ | This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | ||