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subdevices [2021/01/29 13:52] – [UART] ursgraf | subdevices [2021/01/29 13:52] – [UART] ursgraf | ||
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|0xzz|4|rx_0|r|no|uart 0: receive register| | |0xzz|4|rx_0|r|no|uart 0: receive register| | ||
|0xzz+4|4|rx_1|r|no|uart 1: receive register| | |0xzz+4|4|rx_1|r|no|uart 1: receive register| | ||
- | |..|4|..|rw|no|..| | + | |..|4|..|r|no|..| |
|0xuu|4|stat_0|r|no|uart 0: status register| | |0xuu|4|stat_0|r|no|uart 0: status register| | ||
|0xuu+4|4|stat_1|r|no|uart 1: status register| | |0xuu+4|4|stat_1|r|no|uart 1: status register| | ||
- | |..|4|..|rw|no|..| | + | |..|4|..|r|no|..| |
The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | ||