subdevices
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| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision | ||
| subdevices [2021/02/05 07:59] – [UART] ursgraf | subdevices [2021/02/05 08:05] – [UART] ursgraf | ||
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| Line 114: | Line 114: | ||
| |0xuu+4|4|stat_1|r|no|uart 1: status register| | |0xuu+4|4|stat_1|r|no|uart 1: status register| | ||
| |..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
| - | Both the transmit and receive path contain a 1024 entry long FIFO memory. \\ | + | Both the transmit and receive path contain a 1024 entry FIFO memory. \\ |
| - | The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. The status register \\ | + | The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. The status register |
| + | |||
| + | | 31...26 | 25...16 | 15...7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | ||
| + | | unused | number of active entries in rx FIFO |unused|tx FIFO full|tx FIFO half full|tx FIFO empty|unused|rx FIFO full|rx FIFO half full|rx FIFO empty|\\ | ||
| This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel). | ||
subdevices.txt · Last modified: 2024/04/09 20:46 by ursgraf
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