subdevices
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subdevices [2021/02/05 08:05] ursgraf [UART] |
subdevices [2021/02/05 08:06] ursgraf [UART] |
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| |..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
| Both the transmit and receive path contain a 1024 entry FIFO memory. \\ | Both the transmit and receive path contain a 1024 entry FIFO memory. \\ | ||
| - | The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. The status register of each channel | + | The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. The status register of each channel |
| | 31...26 | 25...16 | 15...7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | | 31...26 | 25...16 | 15...7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | ||
| | unused | number of active entries in rx FIFO |unused|tx FIFO full|tx FIFO half full|tx FIFO empty|unused|rx FIFO full|rx FIFO half full|rx FIFO empty|\\ | | unused | number of active entries in rx FIFO |unused|tx FIFO full|tx FIFO half full|tx FIFO empty|unused|rx FIFO full|rx FIFO half full|rx FIFO empty|\\ | ||
subdevices.txt · Last modified: 2021/02/05 08:06 by ursgraf
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