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subdevices [2018/01/30 11:28] sfink [DAC] |
subdevices [2020/06/09 17:24] (current) ursgraf [Watchdog] |
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| |0x20|4|memory size|r|yes|total memory size for the device (in bytes) including all subdevices| | |0x20|4|memory size|r|yes|total memory size for the device (in bytes) including all subdevices| | ||
| |0x24|28|description|r|yes|contains a description, including a name and/or a date| | |0x24|28|description|r|yes|contains a description, including a name and/or a date| | ||
| + | Insert the description in hexadecimal notation, e.g. "ABC" becomes #414243. Enter in the description field with left alingment, e.g. 41424300000000000000000000000000000000000000000000000000 . Use a string to hex converter. | ||
| The status and configuration registers in the subheader are unused with this function. | The status and configuration registers in the subheader are unused with this function. | ||
| ===== ADC ===== | ===== ADC ===== | ||
| - | This function is used to gather analog input data from an ADC. | + | This function is used to gather analog input data from an ADC. The ADC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock. |
| ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ||
| |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
| Line 30: | Line 31: | ||
| |0x28|4|value_1|r|no|channel 1: digitized input value| | |0x28|4|value_1|r|no|channel 1: digitized input value| | ||
| |..|4|..|r/w|no|..| | |..|4|..|r/w|no|..| | ||
| - | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
| ==== Subtypes ==== | ==== Subtypes ==== | ||
| - | Currently there are two subtypes of this subdevice. The subtype information can be found in the ''function'' register of the header. | + | Currently there are three subtypes of this subdevice. The subtype information can be found in the ''function'' register of the header. |
| ^Subtype ID^Description^Example^ | ^Subtype ID^Description^Example^ | ||
| |0x1|Simple ADC with continuous sampling|ADC128S102| | |0x1|Simple ADC with continuous sampling|ADC128S102| | ||
| |0x2|Advanced model with integrated filter and sampling mode selection|AD7606| | |0x2|Advanced model with integrated filter and sampling mode selection|AD7606| | ||
| + | |0x3|Simple ADC, low power|AD7476| | ||
| ===== DAC ===== | ===== DAC ===== | ||
| - | This function serves to drive an DAC. | + | This function serves to drive an DAC. The DAC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock. |
| ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ||
| |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | |0x20|4|resolution|r|yes|this is the number of resolvable digital steps| | ||
| Line 44: | Line 46: | ||
| |0x28|4|value_1|r/w|no|channel 1: digital output value| | |0x28|4|value_1|r/w|no|channel 1: digital output value| | ||
| |..|4|..|r/w|no|..| | |..|4|..|r/w|no|..| | ||
| - | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
| ==== Subtypes ==== | ==== Subtypes ==== | ||
| Currently there is one subtype of this subdevice. The subtype information can be found in the ''unique id'' register of the header. | Currently there is one subtype of this subdevice. The subtype information can be found in the ''unique id'' register of the header. | ||
| Line 61: | Line 63: | ||
| A value of '1' configures a pin as an output in the direction register. | A value of '1' configures a pin as an output in the direction register. | ||
| The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. \\ | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. \\ | ||
| - | At powerup all pins will be inputs. | + | At powerup all pins will be inputs. This subdevice uses a pin on the FPGA device for each channel. |
| ===== Counter ===== | ===== Counter ===== | ||
| - | All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. | + | All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. The counter module implements a 16 bit counter, hence, reading the counter value will return only 2 bytes. |
| ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ||
| |0x20|4|count_0|r|no|counter channel 0| | |0x20|4|count_0|r|no|counter channel 0| | ||
| |0x24|4|count_1|r|no|counter channel 1| | |0x24|4|count_1|r|no|counter channel 1| | ||
| |..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
| - | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses two pins on the FPGA device for each channel. |
| ===== PWM ===== | ===== PWM ===== | ||
| - | Used to output pulse with modulated output signals. | + | Used to output pulse with modulated output signals. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the frequency setting is derived from this clock. |
| ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ||
| |0x20|4|base_clk|r|no|base clock in Hz| | |0x20|4|base_clk|r|no|base clock in Hz| | ||
| Line 81: | Line 83: | ||
| |0xyy+4|4|htime_1|r/w|no|channel 1: high time in multiples of base clock| | |0xyy+4|4|htime_1|r/w|no|channel 1: high time in multiples of base clock| | ||
| |..|4|..|r/w|no|..| | |..|4|..|r/w|no|..| | ||
| - | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
| ===== PPWA ===== | ===== PPWA ===== | ||
| - | This function realizes period and pulse width measurements. | + | This function realizes period and pulse width measurements. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the time measurement is derived from that clock. |
| ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ||
| |0x20|4|base_clk|r|no|base clock in Hz| | |0x20|4|base_clk|r|no|base clock in Hz| | ||
| Line 93: | Line 95: | ||
| |0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | |0xyy+4|4|htime_1|r|no|channel 1: high time in multiples of base clock| | ||
| |..|4|..|r|no|..| | |..|4|..|r|no|..| | ||
| - | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. | + | The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. |
| ===== Watchdog ===== | ===== Watchdog ===== | ||
| - | The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. | + | The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. |
| ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ^Offset^Size [byte] ^Name^r/w^Const^Description^ | ||
| Line 106: | Line 108: | ||
| | 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | | | 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | | ||
| | | | | | | | | |rearm|status| | | | | | | | | | |rearm|status| | ||
| - | status: shows the value of the watchdog signal. If '1': the watchdog-timer is still running and the output is set, if '0': the watchdog has timed out and the output is not set. \\ | + | status: shows the value of the watchdog signal. If '1': the watchdog-timer is still running and the signal ''granted'' is set. If '0': the watchdog has timed out and ''granted'' is not set. \\ |
| rearm: When the watchdog has fired (timed out), it has to be reset with this signal. Write '1' to rearm. This bit is self clearing to '0'.\\ | rearm: When the watchdog has fired (timed out), it has to be reset with this signal. Write '1' to rearm. This bit is self clearing to '0'.\\ | ||
| - | counter: before the watchdog gets rearmed, a counter-value has to be set. | + | counter: set the watchdog timeout before you arm the watchdog. |
| + | === Outputs === | ||
| + | This subdevice uses two pins on the FPGA device. The two output are as follows | ||
| + | * watchdog_pwm: outputs short pulses each time the counter value is reloaded | ||
| + | * granted: outputs logic '1' as long as the watchdog is active. As soon as a timeout occurs, this signals goes to logic '0'. | ||
| ===== Sensor ===== | ===== Sensor ===== | ||
subdevices.1517308111.txt.gz · Last modified: 2018/01/30 11:28 by sfink
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