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Universal Serial Interface to FPGA's

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subdevices [2020/06/09 17:24]
ursgraf [Watchdog] 		subdevices [2021/02/05 08:06] (current)
ursgraf [UART]
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 |0x0c|PWM|pulse width modulated output| |0x0c|PWM|pulse width modulated output|
 |0x0d|PPWA|period and pulse width measurement| |0x0d|PPWA|period and pulse width measurement|
 +|0x0f|UART|serial communication|
 |0x10|Watchdog|watchdog timer| |0x10|Watchdog|watchdog timer|
 |0x11|Sensor|various sensors (inductive, acceleration)| |0x11|Sensor|various sensors (inductive, acceleration)|
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 Used to output pulse with modulated output signals. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the frequency setting is derived from this clock.  Used to output pulse with modulated output signals. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the frequency setting is derived from this clock. 
 ^Offset^Size [byte] ^Name^r/w^Const^Description^ ^Offset^Size [byte] ^Name^r/w^Const^Description^
-|0x20|4|base_clk|r|no|base clock in Hz|+|0x20|4|base_clk|r|yes|base clock in Hz|
 |0x24|4|ptime_0|r/w|no|channel 0: period in multiples of base clock| |0x24|4|ptime_0|r/w|no|channel 0: period in multiples of base clock|
 |0x28|4|ptime_1|r/w|no|channel 1: period in multiples of base clock| |0x28|4|ptime_1|r/w|no|channel 1: period in multiples of base clock|
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 This function realizes period and pulse width measurements. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the time measurement is derived from that clock.  This function realizes period and pulse width measurements. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the time measurement is derived from that clock. 
 ^Offset^Size [byte] ^Name^r/w^Const^Description^ ^Offset^Size [byte] ^Name^r/w^Const^Description^
-|0x20|4|base_clk|r|no|base clock in Hz|+|0x20|4|base_clk|r|yes|base clock in Hz|
 |0x24|4|ptime_0|r|no|channel 0: period in multiples of base clock| |0x24|4|ptime_0|r|no|channel 0: period in multiples of base clock|
 |0x28|4|ptime_1|r|no|channel 1: period in multiples of base clock| |0x28|4|ptime_1|r|no|channel 1: period in multiples of base clock|
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 |..|4|..|r|no|..| |..|4|..|r|no|..|
 The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel.
 +
 +===== UART =====
 +This function implements one or more serial communication interfaces. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the baud rate is derived from that clock. 
 +^Offset^Size [byte] ^Name^r/w^Const^Description^
 +|0x20|4|base_clk|r|yes|base clock in Hz|
 +|0x24|4|devider_0|rw|no|uart 0: clock divider for baud rate|
 +|0x28|4|devider_1|rw|no|uart 1: clock divider for baud rate|
 +|..|4|..|rw|no|..|
 +|0xyy|4|tx_0|rw|no|uart 0: transmit register|
 +|0xyy+4|4|tx_1|rw|no|uart 1: transmit register|
 +|..|4|..|rw|no|..|
 +|0xzz|4|rx_0|r|no|uart 0: receive register|
 +|0xzz+4|4|rx_1|r|no|uart 1: receive register|
 +|..|4|..|r|no|..|
 +|0xuu|4|stat_0|r|no|uart 0: status register|
 +|0xuu+4|4|stat_1|r|no|uart 1: status register|
 +|..|4|..|r|no|..|
 +Both the transmit and receive path contain a 1024 entry FIFO memory. \\
 +The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. The status register of each channel contains the following information
 +| 31...26 | 25...16 | 15...7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
 +| unused | number of active entries in rx FIFO |unused|tx FIFO full|tx FIFO half full|tx FIFO empty|unused|rx FIFO full|rx FIFO half full|rx FIFO empty|\\
 +This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel).
 +
  
 ===== Watchdog ===== ===== Watchdog =====
-The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. +The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. The field ''nofChannels'' will return 1.
  
 ^Offset^Size [byte] ^Name^r/w^Const^Description^ ^Offset^Size [byte] ^Name^r/w^Const^Description^
 |0x20|4|base_clk|r|yes|base clock in Hz| |0x20|4|base_clk|r|yes|base clock in Hz|
-|0x24|4|status_conf|r/w|no|status and configuration register| +|0x24|4|counter|r/w|no|counter|
-|0x28|4|counter|r/w|no|counter|+
  
-=== status_conf === +The last bit in the status register shows the value of the watchdog signal. If '1': the watchdog-timer is still running and the signal ''granted'' is set. If '0': the watchdog has timed out and ''granted'' is not set. \\ 
-| 31 | ... | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | +The last bit in the configuration register holds the rearm bit. When the watchdog has fired (timed out), it has to be reset by setting the rearm bit. Write '1' to rearm. This bit is self clearing to '0'.\\
-| | | | | | | | |rearm|status| +
-status: shows the value of the watchdog signal. If '1': the watchdog-timer is still running and the signal ''granted'' is set. If '0': the watchdog has timed out and ''granted'' is not set. \\ +
-rearm: When the watchdog has fired (timed out), it has to be reset with this signal. Write '1' to rearm. This bit is self clearing to '0'.\\+
 counter: set the watchdog timeout before you arm the watchdog. counter: set the watchdog timeout before you arm the watchdog.
  
 === Outputs === === Outputs ===
 This subdevice uses two pins on the FPGA device. The two output are as follows   This subdevice uses two pins on the FPGA device. The two output are as follows  
-  * watchdog_pwm: outputs short pulses each time the counter value is reloaded+  * watchdog_pwm: this output changes its state each time the counter value is reloaded
   * granted: outputs logic '1' as long as the watchdog is active. As soon as a timeout occurs, this signals goes to logic '0'.   * granted: outputs logic '1' as long as the watchdog is active. As soon as a timeout occurs, this signals goes to logic '0'.
  
subdevices.1591716258.txt.gz · Last modified: 2020/06/09 17:24 by ursgraf

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