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flink_vhdl [2016/06/08 14:21] – [Building] tinner | flink_vhdl [2023/10/12 17:07] – ursgraf | ||
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- | This is the user documentation for the flink VHDL modules. At the current state flink is only available for Altera FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera |
\\ | \\ | ||
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* [[.: | * [[.: | ||
</ | </ | ||
- | * Quartus | + | * Quartus |
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Instead of Altera Quartus, Xilinx | + | * Vivado (Tested |
+ | |||
+ | ===== Id and Unique_Id ===== | ||
+ | Every subdevice has a parameter '' | ||
+ | When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the '' | ||
+ | The '' | ||
+ | An userland application should use '' | ||
+ | |||
+ | ===== Info Subdevice ===== | ||
+ | An info subdevice serves for information purposes only. It comprises the fields '' | ||
+ | \\ | ||
+ | The field '' | ||
+ | |||
===== Building ===== | ===== Building ===== | ||
==== Quartus ==== | ==== Quartus ==== | ||
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- Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | ||
- Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | ||
- | - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them '' | + | - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them '' |
- Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA. | - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA. | ||
- Connect all the clock sinks as well as the reset sinks. | - Connect all the clock sinks as well as the reset sinks. | ||
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- Open Pin Planer and designate all the necessary pins. | - Open Pin Planer and designate all the necessary pins. | ||
- Compile the design and download it. | - Compile the design and download it. | ||
+ | |||
==== Vivado ==== | ==== Vivado ==== | ||
- | - Start Vivado and create a new project. | + | |
- | - Choose your appropriate device. | + | - Choose your appropriate |
+ | - Under //Project Manager// -> // | ||
+ | - Under //Project Manager// -> // | ||
+ | - In the //IP INTEGRATOR// | ||
+ | - Add a ZYNQ7 processor system to the design and click //Run Block Automation// | ||
+ | - Double click on the processor system. In the //clock configuration// | ||
+ | - Add all desired subdevices. Add an //AXI Interconnect// | ||
+ | - Press //Run Connection Automation// | ||
+ | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. | ||
+ | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type // | ||
+ | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | ||
+ | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// | ||
+ | - Change the properties of the infoDevice as follows: //Dev Size// must be the total size of all subdevices combined. Set the description to a meaningful name. | ||
+ | - Right click on your block design and select //Create HDL Wrapper// with //let Vivado manage ...//. | ||
+ | - Under //PROGRAM AND DEBUG// select //Generate Bitstream// | ||
+ | - The resulting FPGA configuration file can be found under // | ||
- | ===== Id and Unique_Id ===== | ||
- | Every subdevice has a parameter '' | ||
- | When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the '' | ||
- | The '' | ||
- | An userland application should use '' | ||
- | |||
- | ===== Info Subdevice ===== | ||
- | An info subdevice serves for information purposes only. It comprises the fields '' | ||
- | \\ | ||
- | The field '' | ||
- | |||