Universal Serial Interface to FPGA's
This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs.
We currently support various functions which are implemented in subdevices. More functions will be developed in the near future.
Every subdevice has a parameter
unique_id. The user can assign any unique value to it. Please keep a list with these values.
When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the
id. A subdevice can now be selected either by its
unique_id or its
unique_id is defined as a parameter when configuring the subdevice in the FPGA. On the other side,
id is set at runtime when subdevices are scanned.
id therefore depends on the arrangement of the subdevices in a device.
unique_id can be kept constant in any arrangement.
An userland application should use
unique_id when searching for a subdevice. This ensures that the application doesn't have to be recompiled when more subdevices are added to a FPGA design and the memory arrangement changes.
An info subdevice serves for information purposes only. It comprises the fields
dev_size and has no channels. It can be included in any design if desired.
dev_size is very handy if the interface to the FPGA doesn't allow for enumeration. In those cases the info subdevice can be queried for this field.
description can be used to ascertain that a specific design is present in the FPGA.
unique_id. Also add an interface module such as a PCI or SPI interface.