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flink_vhdl [2016/06/08 14:48] – [Building] tinner | flink_vhdl [2018/01/29 22:33] – [Building] sfink | ||
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====== VHDL ====== | ====== VHDL ====== | ||
<box blue right 38% | **Downloads**> | <box blue right 38% | **Downloads**> | ||
- | * [[https:// | + | * [[https:// |
</ | </ | ||
- | This is the user documentation for the flink VHDL modules. At the current state flink is only available for Altera FPGAs. | + | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera |
\\ | \\ | ||
\\ | \\ | ||
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* Quartus Version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 | * Quartus Version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 | ||
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Instead of Altera Quartus, Xilinx Vivado can be used. (Only tested | + | * Instead of Altera Quartus, Xilinx Vivado can be used. (Tested |
===== Building ===== | ===== Building ===== | ||
==== Quartus ==== | ==== Quartus ==== | ||
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==== Vivado ==== | ==== Vivado ==== | ||
- Start Vivado and create a new project. | - Start Vivado and create a new project. | ||
- | - Choose your appropriate device. | + | - Choose your appropriate device. If you want a specific board as target, you can choose it from the tab " |
- | - Under Project Settings General tab change | + | - Under „Project |
- | - Under Project Settings | + | - Under „IP“ -> „Repository“ add the flinkvhdl root directory with the (green) blue cross. |
- | - Create | + | - In the "IP INTEGRATOR" |
- | - Add a ZYNQ7 Processor System to the design. | + | - Add a ZYNQ7 Processor System to the design |
- | - Open the IP Catalog and add all needed subdevices found under User Repository-> | + | - Double click the Processor System. In the "clock configuration" |
- | - In the Block Design press Run Block Automation | + | - Open the IP Catalog(blue cross) |
- | | + | - In the Block Design press "Run Connection |
- | - Create | + | - Right click on the ports of the subdevices and create ports nesessary. |
- | - Open the Address Editor and make sure that all devices have a Range of 4K and that there are no gaps between two devices. If a info device | + | - Open the „Address Editor“-tab |
- | - Add pin mapping. | + | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// |
- | - Create Bitstream | + | - Ensure that every fLink Subdevice has its own unique id. |
+ | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096. | ||
+ | - Right click on your Block Design and select "Create | ||
+ | - Under „PROGRAM AND DEBUG“ select „Generate | ||
===== Id and Unique_Id ===== | ===== Id and Unique_Id ===== | ||
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===== Info Subdevice ===== | ===== Info Subdevice ===== | ||
- | An info subdevice serves for information purposes only. It comprises the fields '' | + | An info subdevice serves for information purposes only. It comprises the fields '' |
\\ | \\ | ||
The field '' | The field '' | ||