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flink_vhdl [2018/01/29 21:55] – external edit 127.0.0.1 | flink_vhdl [2023/12/13 07:49] – [Building] ursgraf | ||
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====== VHDL ====== | ====== VHDL ====== | ||
<box blue right 38% | **Downloads**> | <box blue right 38% | **Downloads**> | ||
- | * [[https:// | + | * [[https:// |
</ | </ | ||
- | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
\\ | \\ | ||
\\ | \\ | ||
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* [[.: | * [[.: | ||
</ | </ | ||
- | * Quartus | + | * Quartus |
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Instead of Altera Quartus, Xilinx | + | * Vivado (Tested with Version 2016.1, 2017.3, 2017.4 |
+ | |||
+ | ===== Id and Unique_Id ===== | ||
+ | Every subdevice has a parameter '' | ||
+ | When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the '' | ||
+ | The '' | ||
+ | An userland application should use '' | ||
+ | |||
+ | ===== Info Subdevice ===== | ||
+ | An info subdevice serves for information purposes only. It comprises the fields '' | ||
+ | \\ | ||
+ | The field '' | ||
+ | |||
===== Building ===== | ===== Building ===== | ||
==== Quartus ==== | ==== Quartus ==== | ||
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- Choose your appropriate device. | - Choose your appropriate device. | ||
- Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | ||
- | - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | + | - Start Platform Designer (formerly |
- | - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them '' | + | - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them '' |
- Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA. | - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA. | ||
- Connect all the clock sinks as well as the reset sinks. | - Connect all the clock sinks as well as the reset sinks. | ||
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- Choose // | - Choose // | ||
- Select the tab // | - Select the tab // | ||
- | - Close Qsys and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system. | + | - Close Platform Designer |
- Set the .qip file as // | - Set the .qip file as // | ||
- Select //Analyse and Synthesis// | - Select //Analyse and Synthesis// | ||
- Open Pin Planer and designate all the necessary pins. | - Open Pin Planer and designate all the necessary pins. | ||
- Compile the design and download it. | - Compile the design and download it. | ||
+ | |||
==== Vivado ==== | ==== Vivado ==== | ||
- | - Start Vivado and create a new project. | + | - Start Vivado and create a new project |
- | - Choose your appropriate | + | - Choose your appropriate |
- | - Under „Project Manager“ -> „Settings“ in the „General“ tab change target language to VHDL. | + | - Under //Project Manager// -> //Settings// -> //General// change target language to VHDL. |
- | - Under „IP“ -> „Repository“ add the flinkvhdl root directory | + | - Under //Project Manager// -> // |
- | - In the "IP INTEGRATOR" | + | - In the //IP INTEGRATOR// click // |
- | - Add a ZYNQ7 Processor System | + | - Add a ZYNQ7 processor system |
- | - Open the IP Catalog(blue cross) and add all needed subdevices found under User Repository->fLink-> | + | - Double click on the processor system. In the //clock configuration// |
- | - In the Block Design press "Run Connection Automation" -> add all Subdevices | + | - Add all desired subdevices. Add an //AXI Interconnect// |
- | - Right click on the ports of the subdevices and create | + | - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// |
- | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. | + | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. |
+ | - Right click on the outputs | ||
+ | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. | ||
- Add pin mapping. For specific boards you can get your .xdc-files [[https:// | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// | ||
- | - Ensure that every fLink Subdevice has its own unique id. | + | - Change |
- | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096. | + | - Right click on your block design |
- | - Right click on your Block Design | + | - Under //PROGRAM AND DEBUG// select |
- | - Under „PROGRAM AND DEBUG“ select | + | - The resulting FPGA configuration file can be found under // |
- | ===== Id and Unique_Id ===== | ||
- | Every subdevice has a parameter '' | ||
- | When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the '' | ||
- | The '' | ||
- | An userland application should use '' | ||
- | |||
- | ===== Info Subdevice ===== | ||
- | An info subdevice serves for information purposes only. It comprises the fields '' | ||
- | \\ | ||
- | The field '' | ||
- | |||