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flink_vhdl [2018/01/30 11:11] – [Building] sfink | flink_vhdl [2019/12/12 20:05] – [Requirements] ursgraf | ||
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* [[.: | * [[.: | ||
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- | * Quartus | + | * Quartus |
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Instead of Altera Quartus, Xilinx | + | * Vivado (Tested with Version 2016.1, 2017.3 and 2017.4) |
===== Building ===== | ===== Building ===== | ||
==== Quartus ==== | ==== Quartus ==== | ||
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==== Vivado ==== | ==== Vivado ==== | ||
- Start Vivado and create a new project. | - Start Vivado and create a new project. | ||
- | - Choose your appropriate device. If you want a specific board as target, you can choose it from the tab "Boards". If your board is not listed, you can download the Xilinx-Boards [[https:// | + | - Choose your appropriate device. If you want a specific board as target, you can choose it from the tab //Boards//. If your board is not listed, you can download the Xilinx-Boards [[https:// |
- Under „Project Manager“ -> „Settings“ in the „General“ tab change target language to VHDL. | - Under „Project Manager“ -> „Settings“ in the „General“ tab change target language to VHDL. | ||
- Under „IP“ -> „Repository“ add the flinkvhdl root directory with the (green) blue cross. | - Under „IP“ -> „Repository“ add the flinkvhdl root directory with the (green) blue cross. |