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flink_vhdl [2019/12/12 20:00] – ursgraf | flink_vhdl [2019/12/12 20:05] – [Requirements] ursgraf | ||
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- | * Quartus | + | * Quartus |
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Instead of Altera Quartus, Xilinx | + | * Vivado (Tested with Version 2016.1, 2017.3 and 2017.4) |
===== Building ===== | ===== Building ===== | ||
==== Quartus ==== | ==== Quartus ==== |