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flink_vhdl [2019/12/12 20:13] – [Building] ursgraf | flink_vhdl [2020/05/28 10:11] – [VHDL] ursgraf | ||
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- | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
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==== Quartus ==== | ==== Quartus ==== | ||
- Start Quartus and create a new project. | - Start Quartus and create a new project. | ||
- | - Choose your appropriate | + | - Choose your appropriate |
- Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | ||
- Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | ||
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- Compile the design and download it. | - Compile the design and download it. | ||
==== Vivado ==== | ==== Vivado ==== | ||
- | - Start Vivado and create a new project. | + | - Start Vivado and create a new project |
- | - Choose your appropriate | + | - Choose your appropriate |
- | - Under „Project Manager“ -> „Settings“ in the „General“ tab change target language to VHDL. | + | - Under //Project Manager// -> //Settings// -> //General// change target language to VHDL. |
- | - Under „IP“ -> „Repository“ add the flinkvhdl root directory | + | - Under //Project Manager// -> // |
- | - In the "IP INTEGRATOR" | + | - In the //IP INTEGRATOR// click // |
- | - Add a ZYNQ7 Processor System | + | - Add a ZYNQ7 processor system |
- | - Double click the Processor System. In the "clock configuration" | + | - Double click on the processor system. In the //clock configuration// -> //PL fabric clocks// you can choose the frequency driving the AXI Interface. You should also later enter this value in your flink subdevices as baseclock. |
- | - Open the IP Catalog(blue cross) and add all needed | + | - Add all desired |
- | - In the Block Design press "Run Connection Automation" -> add all Subdevices | + | - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// |
- | - Right click on the ports of the subdevices and create | + | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. |
- | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. | + | - Right click on the outputs |
+ | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. | ||
- Add pin mapping. For specific boards you can get your .xdc-files [[https:// | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// | ||
- | - Ensure that every fLink Subdevice has its own unique id. | + | - Change |
- | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096.[{{ : | + | - Right click on your block design |
- | - Right click on your Block Design | + | - Under //PROGRAM AND DEBUG// select |
- | - Under „PROGRAM AND DEBUG“ select | + | - The resulting FPGA configuration file can be found under // |