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flink_vhdl [2019/12/12 20:38] – [Building] ursgraf | flink_vhdl [2021/01/15 13:09] – [Requirements] ursgraf | ||
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====== VHDL ====== | ====== VHDL ====== | ||
<box blue right 38% | **Downloads**> | <box blue right 38% | **Downloads**> | ||
- | * [[https:// | + | * [[https:// |
</ | </ | ||
- | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
\\ | \\ | ||
\\ | \\ | ||
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* Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices | * Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices | ||
* Modelsim Altera 10.1d (only necessary for simulation of modules) | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
- | * Vivado (Tested with Version 2016.1, 2017.3 | + | * Vivado (Tested with Version 2016.1, 2017.3, 2017.4 |
===== Id and Unique_Id ===== | ===== Id and Unique_Id ===== | ||
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- Add all desired subdevices. Add an //AXI Interconnect// | - Add all desired subdevices. Add an //AXI Interconnect// | ||
- Press //Run Connection Automation// | - Press //Run Connection Automation// | ||
- | - Right click on the ports of the subdevices and create | + | |
- | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. | + | |
+ | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. | ||
- Add pin mapping. For specific boards you can get your .xdc-files [[https:// | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// | ||
- | - Ensure that every fLink Subdevice has its own unique id. | + | - Change |
- | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096.[{{ : | + | - Right click on your block design |
- | - Right click on your Block Design | + | - Under //PROGRAM AND DEBUG// select |
- | - Under „PROGRAM AND DEBUG“ select | + | - The resulting FPGA configuration file can be found under // |