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flink_vhdl [2019/12/12 21:00] – [Building] ursgraf | flink_vhdl [2020/05/28 10:11] – [VHDL] ursgraf | ||
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- | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
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- Add all desired subdevices. Add an //AXI Interconnect// | - Add all desired subdevices. Add an //AXI Interconnect// | ||
- Press //Run Connection Automation// | - Press //Run Connection Automation// | ||
- | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. | + | |
- | - Open the „Address Editor“-tab and make sure that all devices have a Range of 4k and that there are no gaps between two devices. | + | |
+ | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. | ||
- Add pin mapping. For specific boards you can get your .xdc-files [[https:// | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// | ||
- | - Ensure that every fLink Subdevice has its own unique id. | + | - Change |
- | - If an infoDevice is used double click on the IP and add the "Dev Size". Every fLink Subdevice has a dev size of 4096.[{{ : | + | - Right click on your block design |
- | - Right click on your Block Design | + | - Under //PROGRAM AND DEBUG// select |
- | - Under „PROGRAM AND DEBUG“ select | + | - The resulting FPGA configuration file can be found under // |