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--- flink_vhdl [2020/01/27 16:20] – [Building] ursgraf
+++ flink_vhdl [2020/01/27 16:20] – [Building] ursgraf
@@ Line 63: / Line 63: @@
   - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// the process will automatically add an //AXI SmartConnect//, which does not work with our components.
   - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock.
-  - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type //xilinx.com:interface:gpio_rtl.
+  - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type //xilinx.com:interface:gpio_rtl//.
   - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address.
   - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]].

flink-project