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flink_vhdl [2020/01/27 16:20] – [Building] ursgraf | flink_vhdl [2020/05/28 10:11] – [VHDL] ursgraf | ||
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- | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
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- Press //Run Connection Automation// | - Press //Run Connection Automation// | ||
- Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. | ||
- | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type // | + | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type // |
- Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | ||
- Add pin mapping. For specific boards you can get your .xdc-files [[https:// | - Add pin mapping. For specific boards you can get your .xdc-files [[https:// |