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flink_vhdl [2021/02/04 21:37] – [Building] ursgraf | flink_vhdl [2023/10/12 17:07] – ursgraf | ||
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- Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | ||
- Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | ||
- | - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them '' | + | - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them '' |
- Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA. | - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA. | ||
- Connect all the clock sinks as well as the reset sinks. | - Connect all the clock sinks as well as the reset sinks. | ||
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- Open Pin Planer and designate all the necessary pins. | - Open Pin Planer and designate all the necessary pins. | ||
- Compile the design and download it. | - Compile the design and download it. | ||
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==== Vivado ==== | ==== Vivado ==== | ||
- Start Vivado and create a new project (RTL). | - Start Vivado and create a new project (RTL). | ||
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- Add all desired subdevices. Add an //AXI Interconnect// | - Add all desired subdevices. Add an //AXI Interconnect// | ||
- Press //Run Connection Automation// | - Press //Run Connection Automation// | ||
- | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. | + | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. |
- Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type // | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type // | ||
- Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. |