flink-project

Universal Serial Interface to FPGA's

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flink_vhdl [2023/10/12 17:07] – ursgrafflink_vhdl [2023/12/13 09:07] (current) – ursgraf
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 ===== Building ===== ===== Building =====
 ==== Quartus ==== ==== Quartus ====
-  - Start Quartus and create a new project.+  - Start Quartus and create a new project. We use QuartusII Web Edition, though, newer versions work as well.
   - Choose your appropriate device.   - Choose your appropriate device.
   - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later!   - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later!
-  - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section.+  - Start Platform Designer (formerly Qsys) and choose //Tools -> Options//. Press //Add// and choose the flink repository root path. After pressing //Finish// flink should be listed in the library section.
   - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them ''unique_id''. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. Also add an interface module such as a PCI or SPI interface.   - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them ''unique_id''. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. Also add an interface module such as a PCI or SPI interface.
   - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA.   - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA.
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   - Choose //System->Assign Base Addresses//. Make sure that there are no empty spaces between subsequent subdevices.    - Choose //System->Assign Base Addresses//. Make sure that there are no empty spaces between subsequent subdevices. 
   - Select the tab //Generation Writer// on the top and choose VHDL in the Synthesis part. Save the system and click the //Generate// button.   - Select the tab //Generation Writer// on the top and choose VHDL in the Synthesis part. Save the system and click the //Generate// button.
-  - Close Qsys and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system.+  - Close Platform Designer and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system.
   - Set the .qip file as //Top-Level-Entity//.   - Set the .qip file as //Top-Level-Entity//.
   - Select //Analyse and Synthesis//.   - Select //Analyse and Synthesis//.
flink_vhdl.1697123275.txt.gz · Last modified: 2023/10/12 17:07 by ursgraf

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