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Universal Serial Interface to FPGA's

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flink_vhdl

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flink_vhdl [2019/12/12 21:36] – [Building] ursgrafflink_vhdl [2023/12/13 09:07] (current) – ursgraf
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 ====== VHDL ====== ====== VHDL ======
 <box blue right 38% | **Downloads**> <box blue right 38% | **Downloads**>
-  * [[https://github.com/flink-project/flinkvhdl | fLink VHDL Modules on Github]]+  * [[https://github.com/flink-project/flinkvhdl | flink VHDL Modules on Github]]
 </box> </box>
  
-This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs.+This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs.
 \\ \\
 \\ \\
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   * Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices   * Quartus version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 for Altera devices
   * Modelsim Altera 10.1d (only necessary for simulation of modules)   * Modelsim Altera 10.1d (only necessary for simulation of modules)
-  * Vivado (Tested with Version 2016.1, 2017.3 and 2017.4) for Xilinx devices+  * Vivado (Tested with Version 2016.1, 2017.3, 2017.4 and 2019.1) for Xilinx devices
  
 ===== Id and Unique_Id ===== ===== Id and Unique_Id =====
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 ===== Building ===== ===== Building =====
 ==== Quartus ==== ==== Quartus ====
-  - Start Quartus and create a new project.+  - Start Quartus and create a new project. We use QuartusII Web Edition, though, newer versions work as well.
   - Choose your appropriate device.   - Choose your appropriate device.
   - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later!   - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later!
-  - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. +  - Start Platform Designer (formerly Qsys) and choose //Tools -> Options//. Press //Add// and choose the flink repository root path. After pressing //Finish// flink should be listed in the library section. 
-  - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them ''unique_id''.  Also add an interface module such as a PCI or SPI interface.+  - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them ''unique_id''. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. Also add an interface module such as a PCI or SPI interface.
   - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA.   - Add a //info subdevice// if necessary. An //info subdevice// can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA.
   - Connect all the clock sinks as well as the reset sinks.   - Connect all the clock sinks as well as the reset sinks.
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   - Choose //System->Assign Base Addresses//. Make sure that there are no empty spaces between subsequent subdevices.    - Choose //System->Assign Base Addresses//. Make sure that there are no empty spaces between subsequent subdevices. 
   - Select the tab //Generation Writer// on the top and choose VHDL in the Synthesis part. Save the system and click the //Generate// button.   - Select the tab //Generation Writer// on the top and choose VHDL in the Synthesis part. Save the system and click the //Generate// button.
-  - Close Qsys and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system.+  - Close Platform Designer and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system.
   - Set the .qip file as //Top-Level-Entity//.   - Set the .qip file as //Top-Level-Entity//.
   - Select //Analyse and Synthesis//.   - Select //Analyse and Synthesis//.
   - Open Pin Planer and designate all the necessary pins.   - Open Pin Planer and designate all the necessary pins.
   - Compile the design and download it.   - Compile the design and download it.
 +
 ==== Vivado ==== ==== Vivado ====
   - Start Vivado and create a new project (RTL).   - Start Vivado and create a new project (RTL).
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   - In the //IP INTEGRATOR// click //Create Block Design//.   - In the //IP INTEGRATOR// click //Create Block Design//.
   - Add a ZYNQ7 processor system to the design and click //Run Block Automation//.   - Add a ZYNQ7 processor system to the design and click //Run Block Automation//.
-  - Double click on the processor system. In the //clock configuration// -> //PL fabric clocks// you can choose the frequency driving the AXI Interface. You should also later enter this value in your flink subdevices as baseclock.+  - Double click on the processor system. In the //clock configuration// -> //PL fabric clocks// you can choose the frequency driving the AXI Interface. You should also later enter this value in your flink subdevices as baseclock. In the //PS-PL Configuration// add a //M AXI GP0 interface// if not already selected.
   - Add all desired subdevices. Add an //AXI Interconnect// device as well.    - Add all desired subdevices. Add an //AXI Interconnect// device as well. 
   - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// the process will automatically add an //AXI SmartConnect//, which does not work with our components.    - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// the process will automatically add an //AXI SmartConnect//, which does not work with our components. 
-  - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock.  +  - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. If the base clock has to be specified, you must make sure, that it reflects the actual system clock of your FPGA. 
-  - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs.+  - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type //xilinx.com:interface:gpio_rtl//.
   - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address.    - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. 
   - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]].   - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]].
flink_vhdl.1576182997.txt.gz · Last modified: 2019/12/12 21:36 by ursgraf

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