User Tools
flink_vhdl
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision | |||
|
flink_vhdl [2019/12/12 21:35] ursgraf [Building] |
flink_vhdl [2019/12/12 21:36] (current) ursgraf [Building] |
||
|---|---|---|---|
| Line 69: | Line 69: | ||
| - Right click on your block design and select //Create HDL Wrapper// with //let Vivado manage ...//. | - Right click on your block design and select //Create HDL Wrapper// with //let Vivado manage ...//. | ||
| - Under //PROGRAM AND DEBUG// select //Generate Bitstream//. | - Under //PROGRAM AND DEBUG// select //Generate Bitstream//. | ||
| - | - The resulting FPGA configuration file can be found under //project_name//project_name.runs//impl_1//. | + | - The resulting FPGA configuration file can be found under //project_name/project_name/runs/impl_1//. |
flink_vhdl.txt · Last modified: 2019/12/12 21:36 by ursgraf
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 4.0 International
