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flink_vhdl
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flink_vhdl [2019/12/12 21:36] ursgraf [Building] |
flink_vhdl [2020/05/28 10:11] (current) ursgraf [VHDL] |
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| ====== VHDL ====== | ====== VHDL ====== | ||
| <box blue right 38% | **Downloads**> | <box blue right 38% | **Downloads**> | ||
| - | * [[https://github.com/flink-project/flinkvhdl | fLink VHDL Modules on Github]] | + | * [[https://github.com/flink-project/flinkvhdl | flink VHDL Modules on Github]] |
| </box> | </box> | ||
| - | This is the user documentation for the fLink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. | + | This is the user documentation for the flink VHDL modules. At the current state flink is available for Altera and Xilinx FPGAs. |
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| - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// the process will automatically add an //AXI SmartConnect//, which does not work with our components. | - Press //Run Connection Automation// to make necessary connections. If you forgot to add an //AXI Interconnect// the process will automatically add an //AXI SmartConnect//, which does not work with our components. | ||
| - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. | - Edit the subdevices, choose properties such as uniqueId, number of channels or base clock. | ||
| - | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. | + | - Right click on the outputs of the subdevices and choose //Create Port//. Choose port type and vector size. Connect them to the outputs. The ports for a gpio device must be created with //create interface port// and be of type //xilinx.com:interface:gpio_rtl//. |
| - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | - Open the //Address Editor// tab and make sure that all devices have a range of 4k and that there are no gaps between two devices. Make sure that the infoDevice is on the first memory address. | ||
| - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]]. | - Add pin mapping. For specific boards you can get your .xdc-files [[https://reference.digilentinc.com/reference/programmable-logic/zybo/start | here ]]. | ||
flink_vhdl.1576182997.txt.gz · Last modified: 2019/12/12 21:36 by ursgraf
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