The functions given below have so far been implemented as VHDL modules (see flinkVHDL). For all of them a suitable driver is available in the flink Userspace Library and the flinkLite Library.

As described in flink, Universal Serial Interface to FPGA's every subdevice realizes a certain function. The function id together with status and configuration registers can be found in the header and subheader section. Every subdevice has further registers which are specific for a certain function. These registers are described below for the available functions.

This subdevice might be present or not in a device. Its purpose is to indicate the total memory size of the whole device. It further has a 28 bytes description field. This allows for identifying a given design.

Insert the description in hexadecimal notation, e.g. “ABC” becomes #414243. Enter in the description field with left alingment, e.g. 41424300000000000000000000000000000000000000000000000000 . Use a string to hex converter. The status and configuration registers in the subheader are unused with this function.

This function is used to gather analog input data from an ADC. The ADC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock.

The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel.

Currently there are three subtypes of this subdevice. The subtype information can be found in the function register of the header.

This function serves to drive an DAC. The DAC is connected through SPI. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock.

The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel.

Currently there is one subtype of this subdevice. The subtype information can be found in the unique id register of the header.

This function realizes digital inputs and outputs. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because debouncing is derived from that clock.

A value of '1' configures a pin as an output in the direction register. The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice.
At powerup all pins will be inputs. This subdevice uses a pin on the FPGA device for each channel.

All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal. The counter module implements a 16 bit counter, hence, reading the counter value will return only 2 bytes.

The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses two pins on the FPGA device for each channel.

Used to output pulse with modulated output signals. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the frequency setting is derived from this clock.

The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel.

This function realizes period and pulse width measurements. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the time measurement is derived from that clock.

The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel.

This function implements one or more serial communication interfaces. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the baud rate is derived from that clock.

Both the transmit and receive path contain a 1024 entry FIFO memory.
The devider register will devide the base clock and the resulting frequency is the baudrate of the UART. The status register in the subheader is unused with this function. Setting the bit 0 in the configuration register will reset the subdevice. The status register of each channel contains the following information

This subdevice uses a pair of pins (rx / tx) on the FPGA device for each uart (channel).

The watchdog is a decrementing counter which will fire as soon as it reaches 0. The counter decrements with every clock cycle. Is has to be set periodically to a desired value to prevent the watchdog of running out. This preset value determines the watchout time. Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the watchdog timer is derived from that clock. The field nofChannels will return 1.

The last bit in the status register shows the value of the watchdog signal. If '1': the watchdog-timer is still running and the signal granted is set. If '0': the watchdog has timed out and granted is not set.
The last bit in the configuration register holds the rearm bit. When the watchdog has fired (timed out), it has to be reset by setting the rearm bit. Write '1' to rearm. This bit is self clearing to '0'.
counter: set the watchdog timeout before you arm the watchdog.

This subdevice uses two pins on the FPGA device. The two output are as follows

• watchdog_pwm: this output changes its state each time the counter value is reloaded
• granted: outputs logic '1' as long as the watchdog is active. As soon as a timeout occurs, this signals goes to logic '0'.

Currently there are two subtypes of this subdevice. The subtype information can be found in the unique id register of the header.

The status and control register in the subheader are described below.

device_id: Revision ID of Silicon.

configuring: '1' indicates that the fpga is writing data to the sensor during this time the data registers are not updated.

comperator: 1:Proximity data is less than Threshold Low value, 0:Proximity data is more than Threshold High value.

wake_up: 1:Wake-up disabled, 0:Wake-up triggered. Proximity data is more than Threshold High value.

DRDYB: 1:No new data available, 0:Data is ready to be read.

OSC_dead: 1:Indicates oscillator overloaded and stopped, 0:Oscillator working.

NOTE: device_id, comperator, wake_up, DRDYB, OSC_dead are directly maped from the sensors status register. Therefore they are not showing the fpgas internal state.

reset: Resets the functions internal status and reads the actual configuration from the sensor

update_config: If '1' is written the configuration is written to the device. Then the configuration is read from the sensor and the config register inside the FPGA is updated. Writing config data during the configuring bit is set in the status register can lead to invalid behavioral. During this time no new data are sampled. The configuring bit in the status register indicates when the update process is finished. Before updating the configuration the sensor has to be brought into power done mode!

response_time:

000: Reserved, 001: Reserved, 010: 192, 011: 384, 100: 768, 101: 1536, 110: 3072, 111: 6144

amplitude: Sets the oscillation amplitude: 00:1V, 01:2V, 10:4V, 11:Reserved

intb_mode: 000: All modes disabled, 001: Wake-up Enabled on INTB terminal, 010: INTB terminal indicates the status of Comparator output, 100: DRDYB Enabled on INTB terminal

PWD_MODE: 0:Standby mode, 1:Active Mode

The register bank of the LDC1000 is as follows:

This registers are directly mapped to the sensors registers. See ldc1000 datasheet for more information.

This register is directly mapped to the sensors register. See ldc1000 datasheet for more information.

This registers are directly mapped to the sensors registers. See ldc1000 datasheet for more information.

This register is directly mapped to the sensors register. See ldc1000 datasheet for more information.

This register is directly mapped to the sensors register. See ldc1000 datasheet for more information.

The status and control register in the subheader are described below.

reset: Resets the internal state and starts a read of the actual sensor config. configuring will go to '1'.

configuring: '1' indicates that the fpga is writing data to the sensor. After the config is writen to the sensor the fpga will read it back and update the fpga internal config register. All changes on the configuration during this time are discarded. A read of the config register during configuring is '1' can end in getting invalid values. Also during this time the data registers are not updated.

all other: All other bits are described in the MPU9250 register map in the manual.

reset: Resets the functions internal status and reads the actual configuration from the sensor

update_config: If '1' is written the configuration is written to the sensor. During this time no new data are sampled. The configuring bit in the status register indicates when the update process is finished.

The register bank of the LMPU9250 is as follows:

For all data registers only the lower 16 bit are valid.

This funtion ist used to drive refelctive photoelectric sensors. It generates a puls to drive the sensor which is selected by the endcoder signals. Encoder signals has to be encoded befor connecting it to the sensors

Make sure to set the base clock of this subdevice correctly (in Altera or Vivado), because the serial clock is derived from that clock.

The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice.

This subdevice uses tree pins to connect the adc7476. An appropriate number of pins for the decoder ⇒ number_of_sensors = 2^{number_of_decoder_pins} And one Pin for the Puls to drive the Sensors.