Universal Serial Interface to FPGA's
If multiple subdevices of the same type, same number of ports and different
unique_id in addition to a subdevice of the same type and different number of ports is used, an error occurs. The following pages explain, how this error can be resolved.
The synthesis of the system throws following, or similar, errors in Quartus:
Error (10652): VHDL Assertion Statement at test01_gpio_block_0.vhd(55): assertion is false - report "Supplied generics do not match expected generics" (FAILURE or ERROR)
Error (12152): Can't elaborate user hierarchy "test01_gpio_block_0:gpio_block_1"
Because the ports of the subdevice are identical, Qsys creates only one component (block) and uses multiple instances of this component. But each subdevice has a unique id, which is why each subdevice needs a different component. Qsys generates an *.vhd file for each component with a name like
Create the missing components manually and integrate them in the generated system. An existing component can be copied and modified.
Generate the system in Qsys
synthesis, where Qsys created the files for the system
test01_gpio_block_0.vhd. In the following text this file(s) is/are called template.
test01_gpio_block_0.vhdis the original and
test01_gpio_block_1.vhdis the copy
unique_id(in this example it is changed to ‘2’)
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000010"
end entity test01_gpio_block_1;
architecture rtl of test01_gpio_block_1 is
unique_id_check(in this example it is changed to ‘2’)
unique_id_check : if unique_id /= "00000000000000000000000000000010" generate
gpio_block_0 component avalon_gpio_interface
unique_idin the generic map of the component decleration (in this example it is changed to ‘2’)
unique_id => "00000000000000000000000000000010"
At approximately line 10 add a new line for each copy created in the last step. The name and the number of the block have to be adapted.
set_global_assignment -library "test01" -name VHDL_FILE [file join $::quartus(qip_path) "test01_gpio_block_1.vhd"]
component test01_gpio_block_1 is --... shortened ... end component test01_gpio_block_1;
gpio_block_1 : component test01_gpio_block_0
gpio_block_1 : component test01_gpio_block_1